25G Ethernet Intel Stratix 10 FPGA
IP User Guide
Updated for Intel
®
Quartus
®
Prime Design Suite:
18.1
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Contents
Contents
1. About the 25G Ethernet Intel FPGA IP Core.................................................................... 4
1.1. 25G Ethernet Intel FPGA IP Core Supported Features................................................ 7
1.2. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support.....................9
1.2.1. 25G Ethernet Intel FPGA IP Core Device Family Support..................................9
1.2.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support....................... 10
1.3. IP Core Verification.............................................................................................. 10
1.3.1. Simulation Environment............................................................................11
1.3.2. Compilation Checking............................................................................... 11
1.3.3. Hardware Testing..................................................................................... 11
1.4. Performance and Resource Utilization..................................................................... 11
1.5. Release Information............................................................................................. 14
2. Getting Started............................................................................................................. 15
2.1. Installing and Licensing Intel FPGA IP Cores............................................................ 15
2.1.1. Intel FPGA IP Evaluation Mode................................................................... 16
2.2. Specifying the Intel Stratix 10 IP Core Parameters and Options.................................. 18
2.3. Simulating the IP Core..........................................................................................18
2.4. Generated File Structure....................................................................................... 19
2.5. Integrating Your IP Core in Your Design.................................................................. 22
2.5.1. Pin Assignments...................................................................................... 22
2.5.2. Adding the Transceiver PLL .......................................................................22
2.5.3. Adding the External Time-of-Day Module for Variations with 1588 PTP
Feature...................................................................................................24
2.5.4. Placement Settings for the 25G Ethernet Intel FPGA IP Core.......................... 26
2.6. Compiling the Full Design and Programming the FPGA.............................................. 27
3. 25G Ethernet Intel FPGA IP Core Parameters............................................................... 28
4. Functional Description.................................................................................................. 31
4.1. 25G Ethernet Intel FPGA IP Core Functional Description............................................ 31
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath.......................................32
4.1.2. 25 GbE TX PCS........................................................................................ 34
4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath...................................... 34
4.1.4. Link Fault Signaling Interface.....................................................................38
4.1.5. 25 GbE RX PCS........................................................................................40
4.1.6. Flow Control............................................................................................40
4.1.7. 1588 Precision Time Protocol Interfaces...................................................... 43
4.2. User Interface to Ethernet Transmission.................................................................. 52
4.2.1. Order of Transmission...............................................................................52
4.2.2. Bit Order For TX and RX Datapaths.............................................................53
5. Reset............................................................................................................................ 54
6. Interfaces and Signal Descriptions............................................................................... 55
6.1.
6.2.
6.3.
6.4.
6.5.
TX MAC Interface to User Logic..............................................................................56
RX MAC Interface to User Logic..............................................................................58
Transceivers........................................................................................................59
Transceiver Reconfiguration Signals........................................................................ 60
Avalon-MM Management Interface..........................................................................62
25G Ethernet Intel Stratix 10 FPGA IP User Guide
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6.6.
6.7.
6.8.
6.9.
7.1.
7.2.
7.3.
7.4.
7.5.
PHY Interface Signals........................................................................................... 62
1588 PTP Interface Signals....................................................................................64
Miscellaneous Status and Debug Signals................................................................. 69
Reset Signals...................................................................................................... 69
7. Control, Status, and Statistics Register Descriptions.....................................................70
PHY Registers......................................................................................................71
TX MAC Registers.................................................................................................73
RX MAC Registers................................................................................................ 74
Pause/PFC Flow Control Registers...........................................................................75
Statistics Registers...............................................................................................79
7.5.1. TX Statistics Registers.............................................................................. 80
7.5.2. RX Statistics Registers.............................................................................. 83
7.6. 1588 PTP Registers.............................................................................................. 86
7.7. TX Reed-Solomon FEC Registers............................................................................ 89
7.8. RX Reed-Solomon FEC Registers............................................................................ 89
8.1. Error Insertion Test and Debugging........................................................................ 92
9. 25G Ethernet Intel Stratix 10 FPGA IP User Guide Archives.......................................... 93
10. Document Revision History for the 25G Ethernet Intel Stratix 10 FPGA IP User
Guide....................................................................................................................... 94
8. Debugging the Link....................................................................................................... 91
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1. About the 25G Ethernet Intel FPGA IP Core
The Intel
®
Stratix
®
10 25G Ethernet Intel FPGA IP core implements the
25G & 50G
Ethernet Specification, Draft 1.6
from the 25 Gigabit Ethernet Consortium and the
IEEE 802.3by 25Gb Ethernet
specification. The IP core includes an option to support
unidirectional transport as defined in
Clause 66
of the
IEEE 802.3-2012 Ethernet
Standard.
The MAC client side interface for the 25G Ethernet Intel FPGA IP core is a
64-bit Avalon
®
Streaming (Avalon-ST) interface. It maps to one 25.78125 Gbps
transceiver. The IP core optionally includes Reed-Solomon forward error correction
(FEC) for support of direct attach copper (DAC) cable.
IEEE 802.3 Clause 74
KR-FEC is
not supported.
The IP core provides standard media access control (MAC) and physical coding
sublayer (PCS), Reed-Solomon FEC, and PMA functions shown in the following block
diagram. The PHY comprises the PCS, optional Reed-Solomon FEC, and elective PMA.
Figure 1.
25G Ethernet MAC, PCS, and PMA IP Clock Diagram
pll_ref_clk
644.53125 MHz/322.265625 MHz
clk_txmac
Avalon-ST
TX Client Interface
alt_e25_top
390.625 MHz
TX
RS-FEC
(optional)
clk_ref
ATX PLL
tx_serial_clk
12.890625 GHz
TX Serial Interface
TX
Adapter
TX
MAC
TX
PCS
Hard PMA
25.78125 Gbps
Avalon-MM Management
Interface
System Resets
CSR
Reset
Reconfiguration Interface
Avalon-ST
RX Client Interface
clk_rxmac
RX
Adapter
RX
MAC
390.625 MHz
RX
PCS
RX
RS-FEC
(optional)
Hard PMA
25.78125 Gbps
RX Serial Interface
clk_ref
644.53125 MHz/322.265625 MHz
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
1. About the 25G Ethernet Intel FPGA IP Core
UG-20109 | 2018.10.05
Figure 2.
10G/25G Ethernet MAC, PCS, and PMA IP Clock Diagram
pll_ref_clk
644.53125 MHz/322.265625 MHz
clk_txmac
Avalon-ST
TX Client Interface
alt_e25_top
390.625 MHz (25G) / 156.25 MHz (10G)
TX
RS-FEC
(optional)
clk_ref
tx_serial_clk
5.15625 GHz
Hard PMA
25.78125 Gbps/10.3125 GHz
TX Serial Interface
ATX PLL
(25G)
ATX PLL
(10G)
tx_serial_clk
12.890625 GHz
TX
Adapter
TX
MAC
TX
PCS
Avalon-MM Management
Interface
System Resets
CSR
Reset
Reconfiguration Interface
Avalon-ST
RX Client Interface
clk_rxmac
RX
Adapter
RX
MAC
RX
PCS
RX
RS-FEC
(optional)
Hard PMA
25.78125 Gbps/10.3125 GHz
RX Serial Interface
390.625 MHz (25G) / 156.25 MHz (10G)
clk_ref
644.53125 MHz/322.265625 MHz
Figure 3.
25G Ethernet MAC and PCS IP Clock Diagram
pll_ref_clk
644.53125 MHz/322.265625 MHz
clk_txmac
Avalon-ST
TX Client Interface
alt_e25_top
390.625 MHz
TX
MAC
TX
PCS
TX
RS-FEC
(optional)
ATX PLL
tx_serial_clk
12.890625 GHz
To external PHY
tx_clkout
tx_parallel_data[63:0]
tx_control_phy[1:0]
TX
Adapter
Avalon-MM Management
Interface
System Resets
CSR
Reset
Avalon-ST
RX Client Interface
clk_rxmac
RX
Adapter
RX
MAC
390.625 MHz
RX
PCS
RX
RS-FEC
(optional)
rx_parallel_data[63:0]
rx_control_phy[1:0]
rx_clkout
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