3.3V and 5.0V pASIC 2 FPGA
Combining Speed, Density, Low Cost and Flexibility
Rev. E
pASIC 2
HIGHLIGHTS
®
QL2007
Ultimate Verilog/VHDL Silicon Solution
-Abundant, high-speed interconnect eliminates manual routing
-Flexible logic cell provides high efficiency
and
performance
-Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
… 7,000
usable ASICgates,
174 I/O pins
-16-bit counter speeds exceeding 200 MHz
-7,000 usable ASIC gates, 11,000 usable PLD gates, 174 I/Os
-3-layer metal ViaLink
®
process for small die sizes
-100% routable and pin-out maintainable
3
pASIC 2
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell
-High synthesis gate utilization from logic cell fragments
-Full IEEE Standard JTAG boundary scan capability
-Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
-3.3V and 5.0V operation with low standby power
-I/O pin-compatibility between different devices in the same packages
-PCI compliant (at 5.0V), full speed 33 MHz implementations
-High design security provided by security fuses
QL2007
Block Diagram
480
Logic
Cells
3-25
QL2007
PRODUCT
SUMMARY
The QL2007 is a 7,000 usable ASIC gate, 11,000 usable PLD gate member
of the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique
combination of architecture, technology, and software tools to provide high
speed, high usable density, low price, and flexibility in the same devices.
The flexibility and speed make pASIC 2 devices an efficient and high
performance silicon solution for designs described using HDLs such as
Verilog and VHDL, as well as schematics.
The QL2007 contains 480 logic cells. With 174 maximum I/Os, the
QL2007 is available in 84-pin PLCC, 144-pin TQFP, and 208-pin PQFP
packages.
Software support for the complete pASIC families, including the QL2007, is
available through three basic packages. The turnkey QuickWorks
®
package
provides the most complete FPGA software solution from design entry to
logic synthesis (by Synplicity, Inc.), to place and route, to simulation. The
QuickTools
TM
and QuickChip
TM
packages provide a solution for designers
who use Cadence, Mentor, Synopsys, Viewlogic, Veribest, or other third-
party tools for design entry, synthesis, or simulation.
FEATURES
Total of 174 I/O Pins
- 166 bidirectional input/output pins, PCI-compliant at 5.0V
in -1/-2 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pins
Four Low-Skew (less than 0.5ns) Distributed Networks
- Two array networks available to logic cell flip-flop clock, set, and
reset - each driven by an input-only pin
- Two global clock/control networks available to F1 logic input, and
logic cell flip-flop clock, set, reset; input and I/O register clock, reset,
enable; and output enable controls - each driven by an input-only pin,
or any input or I/O pin, or any logic cell output or I/O cell feedback
High Performance
- Input + logic cell + output delays under 6 ns
- Datapath speeds exceeding 225 MHz
- Counter speeds over 200 MHz
3-26
QL2007
PINOUT DIAGRAM
84-PIN PLCC
3
pASIC 2
3-27
QL2007
PINOUT DIAGRAMS
PIN # 109
PIN # 1
144-PIN TQFP
pASIC
QL2007-1PF144C
PIN # 73
PIN # 37
208-PIN PQFP
PIN # 1
PIN # 157
pASIC
QL2007-1PQ208C
PIN # 53
3-28
PIN # 105
QL2007
PQFP 208 and TQFP 144 Pinout Table
208
144
PQFP TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NC
1
2
3
NC
4
5
NC
6
7
NC
NC
8
NC
9
NC
10
11
12
13
NC
14
15
16
17
18
19
20
21
22
23
NC
24
NC
25
NC
26
27
28
NC
NC
29
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I
ACLK / I
VCC
I
GCLK / I
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
208
144
PQFP TQFP
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
30
31
NC
32
33
34
NC
35
36
NC
37
38
39
NC
40
NC
NC
41
42
43
NC
44
45
NC
46
47
48
NC
49
NC
50
51
52
NC
53
54
55
56
NC
57
58
59
Function
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
208
144
PQFP TQFP
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
60
61
NC
62
63
NC
NC
64
NC
65
66
67
NC
NC
68
69
NC
70
71
72
NC
73
NC
74
75
76
77
NC
78
79
80
NC
81
82
NC
83
NC
84
85
NC
86
NC
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
TRSTB
TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
208
144
PQFP TQFP
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
87
88
89
90
91
92
93
94
95
NC
96
NC
97
98
NC
99
NC
100
NC
101
102
103
104
105
106
NC
107
NC
108
NC
109
110
111
NC
112
113
NC
NC
114
115
116
NC
Function
GND
I/O
I
ACLK / I
VCC
I
GCLK / I
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
STM
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
208
144
PQFP TQFP
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
117
118
119
120
NC
NC
121
NC
122
123
124
NC
125
126
127
128
129
NC
130
131
132
NC
133
134
NC
135
136
NC
137
NC
138
139
NC
140
NC
141
142
NC
143
144
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
TDO
I/O
3
pASIC 2
3-29
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