QL3025-1PQ208M datasheet, PDF - EEWORLD Datasheet

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QL3025-1PQ208M: Description60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density; File Size224KB，14 Pages; ManufacturerETC

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QL3025-1PQ208M Overview

60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

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Military Plastic pASIC 3 Family

60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

Military pASIC 3 - 3.3V Family

EVICE

IGHLIGHTS

Device Highlights

Features

EATURES

Total of 180 I/O pins

High Performance and High Density

60,000 Usable PLD Gates with 316 I/Os

16-bit counter speeds over 300 MHZ, data path

speeds over 400 MHz

0.35um four-layer metal non-volatile CMOS

process for smallest die sizes

308 bidirectional input/output pins, PCI-compliant

for 5.0 volt and 3.3 volt buses for -1/-2 speed

grades

8 high-drive input/distributed network pins

Eight Low-Skew Distributed Networks

Easy to Use/Fast Development Cycles

100% routable with 100% utilization and complete

pin-out stability

Variable-grain logic cells provide high performance

and 100% utilization

Comprehensive design tools include high quality

Verilog/VHDL synthesis

Two array clock/control networks available to the

logic cell flip-flop clock, set and reset inputs - each

driven by an input-only pin

Up to six global clock/control networks available

to the logic cell F1, clock, set and reset inputs and

the input and I/O register clock, reset and enable

inputs as well as the output enable control - each

driven by an input-only or I/O pin, or any logic cell

output or I/O cell feedback

Advanced I/O Capabilities

Interfaces with both 3.3 volt and 5.0 volt devices

PCI compliant with 3.3V and 5.0V buses for -1/-2

speed grades

Full JTAG boundary scan

Registered I/O cells with individually controlled

clocks and output enables

High Performance

Input + logic cell + output total delays under 6 ns

Data path speeds exceeding 400 MHz

Counter speeds over 300 MHz

Device

ASIC

Gates

PLD

Gates

Package

Max

I/O

Qualification

Level

Supply

Voltage

QL3012

QL3025

QL3040

QL3060

8,000

16,000

24,000

36,000

12,000

25,000

40,000

60,000

84PLCC

208PQFP

174

3.3V

M = Military Temperature (-55 to +125 degrees C)

TABLE 1: Selector Table

Rev B

8-23

Military Plastic pASIC 3 Family

RODUCT

UMMARY

Product Summary

The pASIC 3 FPGA family features up to 60,000

usable PLD gates. pASIC 3 FPGAs are fabricated

on a 0.35mm four-layer metal process using Quick-

Logic’s patented ViaLink technology to provide a

unique combination of high performance, high den-

sity, low cost, and extreme ease-of-use.

The pASIC 3 product family contains 1,584 logic

cells. With a maximum of 316 I/Os, and is available

in 208-PQFP and 84-PLCC packages.

Software support for the complete pASIC 3 family is

available through three basic packages. The turnkey

QuickWorks

package provides the most complete

FPGA software solution from design entry to logic

synthesis, to place and route, to simulation. The

QuickWorks

-Lite and QuickTools

packages pro-

vide a solution for designers who use Cadence,

Exemplar, Mentor, Synopsys, Synplicity, Viewlogic,

Veribest, or other third-party tools for design entry,

synthesis, or simulation.

INOUT

IAGRAM

84-P

PLCC

Pinout Diagram 68-Pin CPGA

TABLE 2: 84-pin PLCC

8-24

Preliminary

Military Plastic pASIC 3 Family

INOUT

IAGRAM

208-P

PQFP

Pinout Diagram 208-Pin PQFP

Pin #157

Pin #1

pASIC

QL3060-1PQ208M

Pin #53

Pin #105

8-25

Military Plastic pASIC 3 Family

PQFP 208-P

INOUT

ABLE

PQFP 208 Pinout Table

208

PQFP

208

Function

I/O

VCC

I/O

GND

I/O

GND

I/O

GCLK / I

ACLK / I

VCC

GCLK / I

VCC

I/O

GND

I/O

VCC

I/O

208

PQFP

Function

GND

I/O

TDI

I/O

GND

I/O

VCC

I/O

GND

I/O

VCC

I/O

GND

I/O

VCCIO

208

PQFP

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

Function

I/O

GND

I/O

VCC

I/O

TRSTB

TMS

I/O

VCC

I/O

GND

I/O

208

Function

PQFP

125

I/O

126

I/O

127

GND

128

I/O

129

GCLK / I

130

ACLK / I

131

VCC

132

GCLK / I

133

GCLK / I

134

VCC

135

I/O

136

I/O

137

I/O

GND

138

I/O

139

I/O

140

I/O

141

I/O

142

I/O

143

I/O

144

I/O

145

VCC

I/O

146

I/O

147

GND

148

I/O

149

I/O

150

I/O

151

I/O

152

I/O

153

I/O

154

I/O

155

I/O

156

I/O

157

TCK

158

STM

I/O

159

I/O

160

I/O

161

I/O

162

I/O

163

GND

164

I/O

165

VCC

166

I/O

167

I/O

208

PQFP

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

Function

I/O

GND

I/O

GND

VCC

I/O

VCCIO

I/O

GND

I/O

VCC

I/O

TDO

8-26

Preliminary

Military Plastic pASIC 3 Family

ABSOLUTE MAXIMUM RATINGS

VCC Voltage ...........................-0.5 to 4.6V

VCCIO Voltage .......................-0.5 to 7.0V

Input Voltage.............. -0.5 to VCCIO+0.5V

Latch-up Immunity

.................. ±200 mA

DC Input Current

...................... ±20 mA

ESD Pad Protection

....................±

2000V

Storage Temperature .......-65

C to +150

Lead Temperature ...........................300

OPERATING RANGE

Symbol

VCC

VCCIO

Parameter

Supply Voltage

I/O Input Tolerance Voltage

Ambient Temperature

Case Temperature

Delay Factor

-0 Speed Grade

-1 Speed Grade

-2 Speed Grade

Military

Min

Max

3.0

3.6

3.0

5.5

-55

125

0.42

2.03

0.42

1.64

0.42

1.37

Unit

°C

DC CHARACTERISTICS

Symbol

VIH

VIL

VOH

VOL

IOZ

IOS

ICC

ICCIO

Parameter

Input HIGH Voltage

Input LOW Voltage

Output HIGH Voltage

Output LOW Voltage

I or I/O Input Leakage Current

3-State Output Leakage Current

Input Capacitance [2]

Output Short Circuit Current [3]

D.C. Supply Current [4]

D.C. Supply Current on VCCIO

Min

Max

Unit

0.5VCC VCCIO+0.5 V

-0.5

0.3VCC

IOH = -12 mA

2.4

0.9VCC

IOH = -500

µA

IOL = 8 mA [1]

0.45

IOL = 1.5 mA

0.1VCC

VI = VCCIO or GND

-10

µA

VI = VCCIO or GND

-10

µA

VO = GND

-15

-180

VO = VCC

210

VI, VIO = VCCIO or GND 0.50 (typ)

100

µA

Conditions

Notes:

[1] Military devices have 8 mA IOL specifications.

[2] Capacitance is sample tested only. Clock pins are 12 pF maximum.

[3] Only one output at a time. Duration should not exceed 30 seconds.

[4] Maximum ICC is 5 mA for all military grade devices. For AC conditions, contact QuickLogic

customer engineering.

8-27

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