QL12X16B-1CG68M datasheet, PDF

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QL12X16B-1CG68M: DescriptionMilitary 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA; File Size320KB，16 Pages; ManufacturerETC

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QL12X16B-1CG68M Overview

Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA

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Military 5.0V pASIC 1 Family

Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA

Military 5.0V pASIC 1 Family

EVICE

IGHLIGHTS

Device Highlights

Features

EATURES

Total of 180 I/O pins

Very High Speed

ViaLink“ metal-to-metal programmable technol-

ogy, allows counter speeds over 150 MHz and

logic cell delays of under 2 ns at 5V, and over 80

MHz at 3.3V operation.

-172 Bidirectional Input/Output pins

-6 Dedicated Input/High-Drive pins

-2 Clock/Dedicated input pins with fanout-

independent, low-skew clock networks

-PCI 2.1 Compliant I/Os

High Usable Density

Up to a 24-by-32 array of 768 logic cells provides

22,000 usable PLD gates in 208-pin PQFP and

208-pin CQFP packages.

Input + logic cell + output delays under 6 ns

Chip-to-chip operating frequencies up to 110 MHz

Internal state machine frequencies up to 150 MHz

Clock skew < 0.5 ns

Input hysteresis provides high noise immunity

Built-in scan path permits 100% factory testing of

logic and I/O cells and functional testing with Auto-

matic Test Vector Generation (ATVG) software

after programming

208 pin PQFP pin for pin compatible with the

208 CQFP

0.65µ CMOS process with ViaLink programming

technology

PCI-Output Drive

Fully PCI 2.1 compliant input/output capability.

(including drive current)

Device

ASIC

Gates

PLD

Gates

Package

Max

I/O

Qualification

Level

SMD

5962-

QL8x12B

QL12x16B

QL16x24B

QL24x32B

1,000

2,000

4,000

8,000

2,000

4,000

7,000

14,000

68CPGA

84CPGA

144CPGA

160 CQFP

208CQFP

208PQFP

122

180

M, /883

96836

95599

96837

M = Military Temperature (-55 to +125 degrees C)

/883 = MIL-STD-883 qualified

TABLE 1: Selector Table

Rev B

8-7

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