BU-61581V3-100 datasheet, PDF - EEWORLD Datasheet

BU-61581V3-100: DescriptionMil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CDFP70, FP-70; CategoryMicrocontrollers and processors; File Size2MB，39 Pages; ManufacturerData Device Corporation

Download Datasheet Parametric View All

BU-61581V3-100 Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CDFP70, FP-70

Parameter Name	Attribute value
Maker	Data Device Corporation
package instruction	DFP, FL70,1.0
Reach Compliance Code	compliant
Is Samacsys	N
Address bus width	16
boundary scan	NO
letter of agreement	MIL-STD-1553A; MIL-STD-1553B; MCAIR; STANAG-3838
Data encoding/decoding methods	BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.125 MBps
External data bus width	16
JESD-30 code	R-CDFP-F70
length	48.26 mm
low power mode	YES
Number of serial I/Os	2
Number of terminals	70
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Encapsulate equivalent code	FL70,1.0
Package shape	RECTANGULAR
Package form	FLATPACK
power supply	5 V
Certification status	Not Qualified
Maximum seat height	3.81 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
width	25.4 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553
Base Number Matches	1

Difference between sysPhysMemDesc[] and sysStaticTlbDesc[] in BSP: When booting, the sysPhysMemDesc[] array is used to map virtual memory to physical memory. So why is it necessary to map the Effective address of sysStaticTlbDesc[] to the Real address? ?...; chinatonglian Embedded System

Do you know the eight important knowledge points of FPGA design?: 1. Balance and exchange between area and speed The area here refers to the amount of logic resources consumed by a design in the FPGA/CPLD . For FPGA, it can be measured by the consumed FF (flip-flop)...; xyd18025265652 FPGA/CPLD

(Beautiful large picture) Participate in TI's early August seminar and receive a C2000 development board: Participate in TI's seminar in early August and receive a C2000 development board. Event details: https://bbs.eeworld.com.cn/thread-111179-1-1.htmlThe board first arrived at my friend's place and is n...; EEWORLD社区 MCU

Find a job!: Six years of WinCE development experience, all based on arm architecture. Two years of network development and socket programming under winCE, two years of WinCE mobile phone development, ril part, tw...; zyc002002 Embedded System

[Xilinx Technical Q&A] Frequency of back-end placement and routing: Q: How do you determine the highest operating frequency of the system before back-end layout and routing? Is it a gradual increase or is there a calculation formula? After synthesis? The integrated ST...; eeleader FPGA/CPLD

Analysis of the Principle of Radio Frequency Identification Technology: [i] Radio frequency identification (RFID) technology has the characteristics of non-contact, fast reading speed and no wear compared to traditional magnetic card and IC card technology. It has develop...; songbo RF/Wirelessly

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components