CAT5269
Dual Digitally Programmable Potentiometers (DPP™)
with 256 Taps and 2-wire Interface
FEATURES
s
Two linear taper digitally programmable poten-
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
s
Automatic recall of saved wiper settings at
tiometers
s
256 resistor taps per potentiometer
power up
s
2.5 to 6.0 volt operation
s
Standby current less than 1
µ
A
s
1,000,000 nonvolatile WRITE cycles
s
100 year nonvolatile memory data retention
s
24-lead SOIC and TSSOP packages
s
Industrial temperature range
Ω
Ω
s
End to end resistance 50kΩ or 100kΩ
s
Potentiometer control and memory access via
2-wire interface (I
2
C like)
s
Low wiper resistance, typically 100Ω
Ω
s
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
DESCRIPTION
The CAT5269 is two digitally programmable
potentiometers (DPPs™) integrated with control logic
and 18 bytes of NVRAM memory. Each DPP consists of
a series of resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper
outputs with CMOS switches. A separate 8-bit control
register (WCR) independently controls the wiper tap
switches for each DPP. Associated with each wiper
control register are four 8-bit non-volatile memory data
registers (DR) used for storing up to four wiper settings.
Writing to the wiper control register or any of the
non-volatile data registers is via a 2-wire serial bus. On
power-up, the contents of the first data register (DR0)
for each of the four potentiometers is automatically
loaded into its respective wiper control registers.
The CAT5269 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40˚C to 85˚C industrial
operating temperature range and offered in a 24-lead
SOIC and TSSOP packages.
PIN CONFIGURATION
SOIC Package (J, W)
TSSOP Package (U, Y)
NC
A0
NC
NC
NC
NC
VCC
R L0
R H0
RW0
A2
WP
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
CAT 19
5269 18
17
16
15
14
13
A3
SCL
NC
NC
NC
NC
GND
R W1
R H1
R L1
A1
SDA
FUNCTIONAL DIAGRAM
RH0 RH1
SCL
SDA
2-WIRE BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R W0
WP
R W1
A0
A1
A2
A3
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
RL0 RL1
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Document No. 2123, Rev. B
CAT5269
PIN DESCRIPTION
Pin
(SOIC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT5269 serial clock input pin is used to
clock all data transfers into or out of the device.
SDA: Serial Data
The CAT5269 bidirectional serial data pin is
used to transfer data into and out of the device.
The SDA pin is an open drain output and can be
wire-Ored with the other open drain or open
collector I/Os.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A
match in the slave address must be made with
the address input in order to initiate communica-
tion with the CAT5269.
R
H
, R
L
: Resistor End Points
The two sets of R
H
and R
L
pins are equivalent
to the terminal connections on a mechanical
potentiometer.
R
W
:
Wiper
The R
W
pins are equivalent to the wiper terminal
of a mechanical potentiometer.
WP:
Write Protect Input
WP
The
WP
pin when tied low prevents non-volatile
writes to the data registers (change of wiper
control register is allowed) and when tied high or
left floating normal read/write operations are
allowed. See Write Protection on page 7 for
more details.
Name
NC
A0
NC
NC
NC
NC
VCC
R
L0
R
H0
R
W0
A2
WP
SDA
A1
R
L1
R
H1
R
W1
GND
NC
NC
NC
NC
SCL
A3
Function
No Connect
Device Address, LSB
No Connect
No Connect
No Connect
No Connect
Supply Voltage
Low Reference Terminal for Potentiometer 0
High Reference Terminal for Potentiometer 0
Wiper Terminal for Potentiometer 0
Device Address
Write Protection
Serial Data Input/Output
Device Address
Low Reference Terminal for Potentiometer 1
High Reference Terminal for Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
No Connect
No Connect
No Connect
No Connect
Bus Serial Clock
Device Address
DEVICE OPERATION
The CAT5269 is two resistor arrays integrated with a 2-wire serial interface, two 8-bit wiper control registers and eight
8-bit, non-volatile memory data registers. Each resistor array contains 255 separate resistive elements connected in
series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R
H
and
R
L
). The tap positions between and at the ends of the series resistors are connected to the output wiper terminals
(R
W
)by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a
time and is determined by the value of the wiper control register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via the 2-wire bus. Additional instructions allow data to be
transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also,
the device can be instructed to operate in an "increment/decrement" mode.
Document No. 2123, Rev. B
2
CAT5269
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect toV
SS(1)(2)
................ –2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Wiper Current .................................................... +6mA
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Recommended Operating Conditions:
V
CC
= +2.5V to +6.0V
Temperature
Industrial
Min
-40°C
Max
85°C
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
R
POT
R
POT
Parameter
Potentiometer Resistance (100KΩ)
Potentiometer Resistance (50KΩ)
Potentiometer Resistance
Tolerance
R
POT
Matching
Power Rating
I
W
R
W
R
W
V
TERM
V
N
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity
(2)
Relative Linearity
(3)
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Temperature Coefficient of
R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
10/10/25
0.4
+300
20
0.4
+1
+0.2
V
SS
200
100
Min.
Limits
Typ.
100
50
+20
1
50
+3
300
150
V
CC
Max.
Units
kΩ
kΩ
%
%
mW
mA
Ω
Ω
V
nV/√Hz
%
LSB
(4)
LSB
(4)
ppm/˚C
ppm/˚C
pF
MHz
R
w(n)(actual)
-R
(n)(expected)(5)
R
w(n+1)
-[R
w(n)+LSB
]
(5)
(1)
(1)
(1)
R
POT
= 50KΩ
(1)
I
W
= +3mA @ V
CC
= 3V
I
W
= +3mA @ V
CC
= 5V
V
SS
= 0V
(1)
25°C, each pot
Test Conditions
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(4) LSB = R
TOT
/ 255 or (R
H
- R
L
) / 255, single pot
(5) n = 0, 1, 2, ..., 255
3
Document No. 2123, Rev. B
CAT5269
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +6.0V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Power Supply Current
Power Supply Current
Non-volatile WRITE
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3.0V)
Output Low Voltage (V
CC
= 1.8V)
-1
Min
Max
1
5
5
10
10
V
CC
x 0.3
0.4
0.5
V
CC
x 0.7 V
CC
+ 1.0
Units
mA
mA
µA
µA
µA
V
V
V
V
I
OL
= 3 mA
I
OL
= 1.5 mA
Test Conditions
f
SCL
= 400 KHz, SDA Open
V
CC
= 6 V, Input = GND
f
SCK
= 400 KHz, SDA Open
V
CC
= 6 V, Input = GND
V
IN
= GND or V
CC
, SDA Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
CAPACITANCE
T
A
= 25˚C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
IN(1)
Test
Input Capacitance (A0, A1, A2, A3, SCL,
WP)
Max.
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
C
I/O(1)
Input/Output Capacitance (SDA)
A.C. CHARACTERISTICS
2.5V-6.0V
Symbol
f
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Parameter
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition SetupTime (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.6
100
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
Min.
Max.
400
200
1
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Document No. 2123, Rev. B
4
CAT5269
POWER UP TIMING
(1)(2)
Symbol
Parameter
t
PUR
t
PUW
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
XDCP TIMING
Symbol
Parameter
t
WRPO
t
WRL
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
Min
5
5
Max
10
10
Units
µs
µs
WRITE CYCLE LIMITS
Symbol
t
WR
Parameter
Max.
5
Units
ms
Write Cycle Time
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Symbol
N
END(1)
T
DR(1)
V
ZAP(1)
I
LTH(1)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
1,000,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHIGH
tLOW
tR
SDA IN
tAA
SDA OUT
tDH
tBUF
5
Document No. 2123, Rev. B
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