BU-6174X/6184X/6186X
ENHANCED MINIATURE ADVANCED
COMMUNICATIONS ENGINE
[ENHANCED MINI-ACE®/µ-ACE (MICRO-ACE®)]
FEATURES
Make sure the next
Card you purchase
has...
®
•
Fully Integrated 1553A/B Notice 2,
McAir, STANAG 3838 Interface Terminal
•
Compatible with Mini-ACE (Plus)
and ACE Generations
•
Choice of :
-
RT or BC/RT/MT In Same Footprint
- RT or BC/RT/MT with 4K RAM
- BC/RT/MT with 64K RAM, and RAM
parity
•
Choice of 5V or 3.3V Logic
• Package Options:
- 1" Square Ceramic Flat Pack or
Gull Wing
- 0.815" Square BGA (µ-ACE)
DESCRIPTION
The Enhanced Miniature Advanced Communications Engine (Enhanced
Mini-ACE) and µ-ACE (Micro-ACE) family of MIL-STD-1553 terminals provide
complete interfaces between a host processor and a 1553 bus, and integrate
dual transceiver, protocol logic, and 4K or 64K words of RAM.
At 0.815" square, the µ-ACE (BGA package) option provides the smallest
footprint in the industry.
The terminals are powered by a choice of 5V or 3.3V logic. Multiprotocol sup-
port of MIL-STD-1553A/B and STANAG 3838, including versions incorporat-
ing McAir compatible transmitters, is provided. There is a choice of 10, 12, 16,
or 20 MHz clocks. The BC/RT/MT versions with 64K words of RAM include
built-in RAM parity checking.
BC features include a built-in message sequence control engine, with a set
of 20 instructions. This feature provides an autonomous means of implement-
ing multi-frame message scheduling, message retry schemes, data double
buffering, asynchronous message insertion, and reporting to the host CPU.
The Enhanced Mini-ACE/µ-ACE incorporates a fully autonomous built-in self-
test, providing comprehensive testing of the internal protocol logic and/or
RAM.
The RT offers the same choices of subaddress buffering as the ACE and
Mini-ACE (Plus), along with a global circular buffering option, 50% rollover
interrupt for circular buffers, an interrupt status queue, and an "Auto-boot"
option to support MIL-STD-1760.
The terminals provide the same flexibility in host interface configurations as
the ACE/Mini-ACE, along with a reduction in the host processor's worst case
holdoff time. Most software features are compatible with the previous genera-
tions of the Mini-ACE (Plus) and ACE series.
•
5V Transceiver with 1760 and McAir
Compatible Options
•
Comprehensive Built-In Self-Test
•
Flexible Processor/Memory Interface,
with Reduced Host Wait Time
•
Choice of 10, 12, 16, or 20 MHz Clock
•
Highly Autonomous BC with
Built-In Message Sequence Control:
- Frame Scheduling
- Branching
- Asynchronous Message Insertion
- General Purpose Queue
- User-defined Interrupts
•
Advanced RT Functions
- Global Circular Buffering
- Interrupt Status Queue
- 50% Circular Buffer Rollover
Interrupts
•
Selective Message Monitor
- Selection by Address, T/R Bit,
Subaddress
- Command and Data Stacks
- 50% and 100% Stack Rollover
Interrupts
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
©
2000 Data Device Corporation
Data Device Corporation
www.ddc-web.com
SHARED
RAM
(1)
TRANSCEIVER
A
DATA BUS
D15-D0
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
ADDRESS BUS
ADDRESS
BUFFERS
DATA
BUFFERS
PROCESSOR
DATA BUS
A15-A0
PROCESSOR
ADDRESS BUS
TRANSCEIVER
B
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
RTAD4-RTAD0, RTADP
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
NOTE 1: See Ordering Information for Available Memory Options.
NOTE 2: Indicates signals brought out only on µ-ACE (BGA package) version.
TX/RX_A
CH. A
TX/RX_A
TX/RX_B
CH. B
2
TX/RX_B
RT ADDRESS
INCMD/MCRST, INCMD
(2)
, MCRST
(2)
MISCELLANEOUS
CLK_IN, TAG_CLK
(2)
,
MSTCLR, SSFLAG/EXT_TRG, TX-INH_A, TX-INH_B,
UPADDREN, RSBITEN
(2)
BU-6174X/6184X/6186X
Y-6/08-0
FIGURE 1. EnhancEd MInIatURE advancEd coMMUnIcatIons EnGInE BLocK dIaGRaM
taBLE 1. EnhancEd MInI-acE/µ-acE sERIEs
sPEcIFIcatIons
PaRaMEtER
aBsoLUtE MaXIMUM RatInG
Supply Voltage
•
Logic +5V or +3.3V
•
RAM +5V
•
Transceiver +5V (Note 12)
Logic
•
Voltage Input Range for +5V
Logic (BU-61XX0/5)
•
Voltage Input Range for +3.3V
Logic (BU-61XX0/3/5)
REcEIvER
Differential Input Resistance
(Notes 1-6)
Differential Input Capacitance
(Notes 1-6)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
tRansMIttER
Differential Output Voltage
•
Direct Coupled Across 35
Ω,
Measured on Bus
•
Transformer Coupled Across
70
Ω,
Measured on Bus
(BU-61XXXXX-XX0,
BU-61XXXXX-XX2) (Note 13)
Output Noise, Diff (Direct Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
(BU-61XXXX3,
BU-61XXXX4)
LoGIc
V
IH
All signals except CLK_IN
CLK_IN
V
IL
All signals except CLK_IN
CLK_IN
Schmidt Hysteresis
All signals except CLK_IN
CLK_IN
I
IH,
I
IL
All signals except CLK_IN
I
IH
(Vcc=5.25V, V
IN
=Vcc)
I
IH
(Vcc=5.25V, V
IN
=2.7V)
I
IH
(Vcc=3.6V, V
IN
=Vcc)
I
IH
(Vcc=3.6V, V
IN
=2.7V)
I
IL
(Vcc=5.25V, V
IN
=0.4V)
I
IL
(Vcc=3.6V, V
IN
=0.4V)
CLK_IN
I
IH
I
IL
V
OH
(Vcc=4.5V, V
IH
=2.7V,
V
IL
=0.2V, I
OH
=max)
V
OH
(Vcc=3.0V, V
IH
=2.7V,
V
IL
=0.2V, I
OH
=max)
V
OL
(Vcc=4.5V, V
IH
=2.7V,
V
IL
=0.2V, I
OL
=max)
V
OL
(Vcc=3.0V, V
IH
=2.7V,
V
IL
=0.2V, I
OL
=max)
I
OL
(Vcc=4.5V)
I
OH
(Vcc=4.5V)
I
OL
(Vcc=3.0V)
I
OH
(Vcc=3.0V)
MIn
tYP
MaX
UnIts
taBLE 1. EnhancEd MInI-acE/µ-acE sERIEs
sPEcIFIcatIons (cont.)
PaRaMEtER
LoGIc (cont)
C
I
(Input Capacitance)
C
IO
(Bi-directional signal input
capacitance)
PoWER sUPPLY REQUIREMEnts
Voltages/Tolerances
•
+5V (RAM for 61860/4/5),
Logic for BU-61XX5) (Note 12)
•
+3.3V (Logic for BU-61XX0/3/4)
(Note 12)
•
+5V (Ch. A, Ch. B)
Current Drain (Total Hybrid)
•
BU-61865XX-XX0
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61865/0X3-XX2
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61864XX-XX0
+5V (RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
•
BU-61864/0X3-XX2
+5V (RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
•
BU-61745XX-XX0. BU-61845XX-XX0
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61745/0X3-XX2,
BU-61845/0X3-XX2
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61743XX-XX0, BU-61843XX-XX0
+5V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
•
BU-61743/0X3-XX2,
BU-61843/0X3-XX2
+5V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
MIn
tYP
50
50
MaX
UnIts
pF
pF
-0.3
-0.3
-0.3
-0.3
-0.3
6.0
6.0
7.0
6.0
6.0
V
V
V
V
V
4.5
3.0
4.75
5.0
3.3
5.0
5.5
3.6
5.25
V
V
V
2.5
5
0.200
0.860
10
kΩ
pF
Vp-p
Vpeak
116
217
318
519
116
228
340
563
66
163
260
454
25
66
174
282
498
25
116
222
328
540
180
285
390
600
180
296
412
645
120
225
330
540
40
120
236
352
585
40
160
265
370
580
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
6
7
9
Vp-p
18
20
-250
100
200
20
22
27
27
10
250
300
300
Vp-p
Vp-p
mVp-p
mV
p
nsec
nsec
150
250
2.1
0.8•V
cc
0.7
0.2•Vcc
0.4
1.0
-10
-350
-10
-350
-350
-350
-10
-10
2.4
2.4
0.4
0.4
3.4
-3.4
2.2
-2.2
10
-50
10
-33
-50
-33
10
10
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
V
V
V
V
mA
mA
mA
mA
116
233
350
584
65
169
273
481
25
160
276
392
625
100
205
310
520
40
mA
mA
mA
mA
mA
mA
mA
mA
mA
65
180
295
525
25
100
216
332
565
40
mA
mA
mA
mA
mA
Data Device Corporation
www.ddc-web.com
3
BU-6174X/6184X/6186X
Y-6/08-0
taBLE 1. EnhancEd MInI-acE/µ-acE sERIEs
sPEcIFIcatIons (cont.)
PaRaMEtER
PoWER dIssIPatIon
(NOTE 14)
Total Hybrid
•
BU-61865XX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61865/0X3-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61864XX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61864/0X3-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61745XX-XX0, BU-61845XX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-61745/0X3-XX2,
BU-61845/0X3-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61743XX-XX0, BU-61843XX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61743/0X3-XX2,
BU-61843/0X3-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die
•
BU-61XXXXX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61XXXX3-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
cLocK InPUt
Frequency
•
Nominal Value
• Default Mode
• Option
• Option
• Option
•
Long Term Tolerance
• 1553A Compliance
• 1553B Compliance
MIn
tYP
MaX
UnIts
taBLE 1. EnhancEd MInI-acE/µ-acE sERIEs
sPEcIFIcatIons (cont.)
PaRaMEtER
cLocK InPUt (cont)
•
Short Term Tolerance, 1 second
• 1553A Compliance
• 1553B Compliance
•
Duty Cycle
1553 MEssaGE tIMInG
Completion of CPU Write
(BC Start)-to-Start of First Message
(for Non-enhanced BC Mode)
BC Intermessage Gap (Note 8)
Non-enhanced
(Mini-ACE compatible) BC mode
Enhanced BC mode (Note 9)
BC/RT/MT Response Timeout (Note 10)
•
18.5 nominal
•
22.5 nominal
•
50.5 nominal
•
128.0 nominal
RT Response Time
(mid-parity to mid-sync) (Note 11)
Transmitter Watchdog Timeout
thERMaL
Operating Case/Ball Temperature
-1XX, -4XX
-2XX, -5XX
-3XX, -8XX
-EXX
Storage Temperature
soLdERInG
Flat Pack/Gull Wing
Lead Temperature (soldering, 10 sec.)
128-ball BGa Package
Maximum peak temperature of Solder
Reflow Profile
Thermal Resistance
Enhanced Mini-acE
Ceramic Flat pack / Gull Wing package
Junction-to-Case, Hottest Die (θ
JC
)
µ-acE
BGA package
(see Thermal Management Section)
Junction-to-Balls, Hottest Die (θ
JB
)
PhYsIcaL chaRactERIstIcs
Size
Enhanced Mini-acE
Ceramic Flat pack / Gull Wing package
µ-acE
BGA package
µ-acE Moisture sensitivity Level
MIn
tYP
MaX UnIts
0.64
0.93
1.22
1.80
0.64
0.99
1.33
2.03
0.44
0.75
1.05
1.66
0.44
0.80
1.17
1.89
0.64
0.93
1.22
1.81
0.64
0.99
1.34
2.04
0.41
0.70
0.94
1.40
0.41
0.72
0.97
1.45
0.18
0.42
0.66
1.14
0.18
0.48
0.78
1.39
0.99
1.22
1.45
1.90
0.99
1.28
1.58
2.16
0.80
1.03
1.26
1.71
0.80
1.09
1.39
1.97
0.88
1.11
1.33
1.97
0.88
1.17
1.46
2.05
0.63
0.85
1.07
1.51
0.63
0.86
1.09
1.56
0.28
0.51
0.75
1.22
0.28
0.58
0.88
1.48
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
-0.001
-0.01
40
2.5
0.001
0.01
60
%
%
%
µs
9.5
10.0
to
10.5
17.5
21.5
49.5
127
4
18.0
22.5
50.5
129.5
660.5
19.5
23.5
51.5
131
7
µs
µs
µs
µs
µs
µs
µs
µs
-55
-40
0
-40
-65
+125
+85
+70
+100
+150
°C
°C
°C
°C
°C
+300
+260
°C
°C
9
11
°C/W
18
22
°C/W
1.0 X 1.0 X 0.155
(25.4 x 25.4 x 3.94)
in.
(mm)
0.815 X 0.815 X 0.120
in.
(20.7 x 20.7 x 3.05) (mm)
MSL-3
16.0
12.0
10.0
20.0
-0.01
-0.10
0.01
0.10
MHz
MHz
MHz
MHz
%
%
Weight
Enhanced Mini-acE
Ceramic Flat pack / Gull Wing package
µ-acE
BGA package
0.6
(17)
.088
(2.5)
oz
(g)
oz
(g)
Data Device Corporation
www.ddc-web.com
4
BU-6174X/6184X/6186X
Y-6/08-0
taBLE 1 notEs:
Notes 1 through 6 are applicable to the Receiver Differential Resistance
and Differential Capacitance specifications:
1. Specifications include both transmitter and receiver (tied together
internally).
2. Impedance parameters are specified directly between pins TX/
RX_A(B) and TX/RX_A(B) of the Enhanced Mini-ACE/µ-ACE
hybrid.
3. It is assumed that all power and ground inputs to the hybrid are
connected.
4. The specifications are applicable for both unpowered and powered
conditions.
5. The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
6. Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
7. Assumes a common mode voltage within the frequency range of
dc to 2 MHz, applied to pins of the isolation transformer on the
stub side (either direct or transformer coupled), and referenced to
hybrid ground. Transformer must be a DDC recommended trans-
former or other transformer that provides an equivalent minimum
CMRR.
8. Typical value for minimum intermessage gap time. Under software
control, this may be lengthened (to 65,535 ms - message time) in
increments of 1 µs. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic "1", then host accesses
during BC Start-of-Message (SOM) and End-of-Message (EOM)
transfer sequences could have the effect of lengthening the inter-
message gap time. For each host access during an SOM or EOM
sequence, the intermessage gap time will be lengthened by 6
clock cycles. Since there are 7 internal transfers during SOM and
5 during EOM, this could theoretically lengthen the intermessage
gap by up to 72 clock cycles; i.e., up to 7.2 ms with a 10 MHz
clock, 6.0 µs with a 12 MHz clock, 4.5 µs with a 16 MHz clock, or
3.6 µs with a 20 MHz clock.
9. For Enhanced BC mode, the typical value for intermessage gap
time is approximately 10 clock cycles longer than for the non-
enhanced BC mode. That is, an addition of 1.0 µs at 10 MHz, 833
ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.
10. Software programmable (4 options). Includes RT-to-RT Timeout
(measured mid-parity of transmit Command Word to mid-sync of
transmitting RT Status Word).
11. Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
12. External 10 µF tantalum and 0.1 µF capacitors should be located
as close as possible to input signals “+5V Vcc CH A” and “+5V
Vcc CH B”, and a 0.1 µF to input signal “+5V/+3.3V Logic”. For the
BU-61864 and BU-61865, and BU-61860 versions, there should
also be a 0.1 µF capacitor for the input signal “+5V RAM”.
13. MIL-STD-1760 requires a 20 Vp-p minimum output on the stub
connection.
14. Power dissipation specifications assume a transformer coupled
configuration with external dissipation (while transmitting) of:
0.14 watts for the active isolation transformer,
0.08 watts for the active bus coupling transformer,
0.45 watts for each of the two bus isolation resistors and
0.15 watts for each of the two bus termination resistors.
IntRodUctIon
The BU-61740/61743/61745 RT, and BU-61840/61843/61845/
61860/61864/61865 BC/RT/MT Enhanced Mini-ACE/µ-ACE family
of MIL-STD-1553 terminals comprise a complete integrated inter-
face between a host processor and a MIL-STD-1553 bus. The
Enhanced Mini-ACE is available as a 1.0 square inch flat pack or
gull wing package. The µ-ACE is available as a 0.815 square inch
BGA package. These terminals are nearly 100% software compat-
ible with the previous generation Mini-ACE and Mini-ACE Plus
terminals, and are software compatible with the original ACE
series.
The Enhanced Mini-ACE provides complete multiprotocol support
of MIL-STD-1553A/B/McAir and STANAG 3838. All versions inte-
grate a dual transceiver, along with protocol, host interface, memory
management logic, and either 4K or 64K words of RAM. In addition,
the BU-61864 and BU-61865 BC/RT/MT terminals include 64K
words of internal RAM, with built-in parity checking.
The Enhanced Mini-ACE includes a 5V voltage source trans-
ceiver for improved line driving capability, with options for MIL-
STD-1760 and McAir compatibility, and the µ-ACE is MIL-
STD-1760 compatible. As a means of reducing power consump-
tion, there are versions for which the logic is powered by 3.3V,
rather than 5V. To provide further flexibility, the Enhanced Mini-
ACE/µ-ACE may operate with a choice of 10, 12, 16, or 20 MHz
clock inputs.
One of the new salient features of the Enhanced Mini-ACE/µ-ACE
is its Enhanced bus controller architecture. The Enhanced BC's
highly autonomous message sequence control engine provides
a means for offloading the host processor for implementing multi-
frame message scheduling, message retry schemes, data dou-
ble buffering, and asynchronous message insertion. For the
purpose of performing messaging to the host processor, the
Enhanced BC mode includes a General Purpose Queue, along
with user-defined interrupts.
A second major new feature of the Enhanced Mini-ACE/µ-ACE is
the incorporation of a fully autonomous built-in self-test. This test
provides comprehensive testing of the internal protocol logic. A
separate test verifies the operation of the internal RAM. Since
the self-tests are fully autonomous, they eliminate the need for
the host to write and read stimulus and response vectors.
The Enhanced Mini-ACE/µ-ACE RT offers the same choices of
single, double, and circular buffering for individual subaddresses
as ACE and Mini-ACE (Plus). New enhancements to the RT
architecture include a global circular buffering option for multiple
(or all) receive subaddresses, a 50% rollover interrupt for circular
buffers, an interrupt status queue for logging up to 32 interrupt
events, and an option to automatically initialize to RT mode with
the Busy bit set. The interrupt status queue and 50% rollover
interrupt features are also included as improvements to the
Enhanced Mini-ACE/µ-ACE's Monitor architecture.
Data Device Corporation
www.ddc-web.com
5
BU-6174X/6184X/6186X
Y-6/08-0
FPGA/CPLD
京公网安备 11010802033920号
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