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71P72604S167BQG8

Description
CABGA-165, Reel
Categorystorage    storage   
File Size233KB,21 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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71P72604S167BQG8 Overview

CABGA-165, Reel

71P72604S167BQG8 Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeCABGA
package instruction13 X 15 MM, 1 MM PITCH, GREEN, FBGA-165
Contacts165
Manufacturer packaging codeBQG165
Reach Compliance Codeunknown
ECCN code3A991
Is SamacsysN
Maximum access time0.5 ns
Other featuresPIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)167 MHz
I/O typeSEPARATE
JESD-30 codeR-PBGA-B165
JESD-609 codee1
length15 mm
memory density18874368 bit
Memory IC TypeQDR SRAM
memory width36
Humidity sensitivity level3
Number of functions1
Number of terminals165
word count524288 words
character code512000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTBGA
Encapsulate equivalent codeBGA165,11X15,40
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply1.5/1.8,1.8 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum standby current0.3 A
Minimum standby current1.7 V
Maximum slew rate0.85 mA
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width13 mm
Base Number Matches1
18Mb Pipelined
QDR™II SRAM
Burst of 2
Features
IDT71P72804
IDT71P72604
Description
The IDT QDRII
TM
Burst of two SRAMs are high-speed synchro-
nous memories with independent, double-data-rate (DDR), read and
write data ports. This scheme allows simultaneous read and write
access for the maximum device throughput, with two data items passed
with each read or write. Four data word transfers occur per clock
cycle, providing quad-data-rate (QDR) performance. Comparing this
with standard SRAM common I/O (CIO), single data rate (SDR) de-
vices, a four to one increase in data access is achieved at equivalent
clock speeds. Considering that QDRII allows clock speeds in excess of
standard SRAM devices, the throughput can be increased well beyond
four to one in most applications.
Using independent ports for read and write data access, simplifies
system design by eliminating the need for bi-directional buses. All buses
associated with the QDRII are unidirectional and can be optimized for
signal integrity at very high bus speeds. The QDRII has scalable output
impedance on its data output bus and echo clocks, allowing the user to
tune the bus for low noise and high performance.
The QDRII has a single DDR address bus with multiplexed read
and write addresses. All read addresses are received on the first half of
the clock cycle and all write addresses are received on the second half
of the clock cycle. The read and write enables are received on the first
half of the clock cycle. The byte and nibble write signals are received on
both halves of the clock cycle simultaneously with the data they are
controlling on the data input bus.
18Mb Density (1Mx18, 512kx36)
Separate, Independent Read and Write Data Ports
-
Supports concurrent transactions
Dual Echo Clock Output
2-Word Burst on all SRAM accesses
DDR (Double Data Rate) Multiplexed Address Bus
-
One Read and One Write request per clock cycle
DDR (Double Data Rate) Data Buses
-
Two word burst data per clock on each port
-
Four word transfers per clock cycle (2 word bursts
on 2 ports)
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
Scalable output drivers
-
Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
-
Output Impedance adjustable from 35 ohms to 70
ohms
Commercial and Industrial Temperature Ranges
1.8V Core Voltage (V
DD
)
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
Functional Block Diagram
(Note1)
D
(Note1)
DATA
REG
DATA
REG
(Note1)
WRITE DRIVER
SA
OUTPUT SELECT
(Note2)
SENSE AMPS
OUTPUT REG
ADD
REG
(Note2)
WRITE/READ DECODE
R
W
BWx
(Note3)
CTRL
LOGIC
18M
MEMORY
ARRAY
(Note4)
(Note4)
(Note1)
Q
K
K
C
C
CLK
GEN
SELECT OUTPUT CONTROL
6109 drw 16
CQ
CQ
Notes
1) Represents 18 signal lines for x18, and 36 signal lines for x36
2) Represents 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 2 signal lines for x18, and 4r signal lines for x36.
4) Represents 36 signal lines for x18, and 72 signal lines for x36.
1
©2005 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
OCTOBER 2008
DSC-6109/0A

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Description CABGA-165, Reel CABGA-165, Reel CABGA-165, Tray
Brand Name Integrated Device Technology Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free Lead free
Is it Rohs certified? conform to conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code CABGA CABGA CABGA
package instruction 13 X 15 MM, 1 MM PITCH, GREEN, FBGA-165 13 X 15 MM, 1 MM PITCH, GREEN, FBGA-165 13 X 15 MM, GREEN, FPBGA-165
Contacts 165 165 165
Manufacturer packaging code BQG165 BQG165 BQG165
Reach Compliance Code unknown unknown unknown
ECCN code 3A991 3A991 3A991
Is Samacsys N N N
Maximum access time 0.5 ns 0.45 ns 0.5 ns
Other features PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK) 167 MHz 200 MHz 167 MHz
I/O type SEPARATE SEPARATE SEPARATE
JESD-30 code R-PBGA-B165 R-PBGA-B165 R-PBGA-B165
JESD-609 code e1 e1 e1
length 15 mm 15 mm 15 mm
memory density 18874368 bit 18874368 bit 18874368 bit
Memory IC Type QDR SRAM QDR SRAM QDR SRAM
memory width 36 36 18
Humidity sensitivity level 3 3 3
Number of functions 1 1 1
Number of terminals 165 165 165
word count 524288 words 524288 words 1048576 words
character code 512000 512000 1000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 70 °C 70 °C 85 °C
organize 512KX36 512KX36 1MX18
Output characteristics 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TBGA TBGA TBGA
Encapsulate equivalent code BGA165,11X15,40 BGA165,11X15,40 BGA165,11X15,40
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form GRID ARRAY, THIN PROFILE GRID ARRAY, THIN PROFILE GRID ARRAY, THIN PROFILE
Parallel/Serial PARALLEL PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) 260 260 260
power supply 1.5/1.8,1.8 V 1.5/1.8,1.8 V 1.5/1.8,1.8 V
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm 1.2 mm
Maximum standby current 0.3 A 0.335 A 0.35 A
Minimum standby current 1.7 V 1.7 V 1.7 V
Maximum slew rate 0.85 mA 0.95 mA 0.7 mA
Maximum supply voltage (Vsup) 1.9 V 1.9 V 1.9 V
Minimum supply voltage (Vsup) 1.7 V 1.7 V 1.7 V
Nominal supply voltage (Vsup) 1.8 V 1.8 V 1.8 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL INDUSTRIAL
Terminal surface Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form BALL BALL BALL
Terminal pitch 1 mm 1 mm 1 mm
Terminal location BOTTOM BOTTOM BOTTOM
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 13 mm 13 mm 13 mm
Base Number Matches 1 1 1
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