709279S6G datasheet, PDF - EEWORLD Datasheet

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709279S6G: DescriptionDual-Port SRAM, 32KX16, 15ns, CMOS, CPGA108, PGA-108; Categorystorage storage; File Size192KB，17 Pages; ManufacturerIDT (Integrated Device Technology)

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709279S6G Overview

Dual-Port SRAM, 32KX16, 15ns, CMOS, CPGA108, PGA-108

709279S6G Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	PGA
package instruction	PGA-108
Contacts	108
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Is Samacsys	N
Maximum access time	15 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 code	S-CPGA-P108
JESD-609 code	e0
memory density	524288 bit
Memory IC Type	DUAL-PORT SRAM
memory width	16
Number of functions	1
Number of terminals	108
word count	32768 words
character code	32000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX16
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	PIN/PEG
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	30
Base Number Matches	1

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HIGH-SPEED 32/16K x 16

SYNCHRONOUS

DUAL-PORT STATIC RAM

Features

◆

IDT709279/69S/L

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial: 9/12/15ns (max.)

– Industrial: 12ns (max.)

Low-power operation

– IDT709279/69S

Active: 950mW (typ.)

Standby: 5mW (typ.)

– IDT709279/69L

Active: 950mW (typ.)

Standby: 1mW (typ.)

Flow-Through or Pipelined output mode on either port via

the

FT/PIPE

Dual chip enables allow for depth expansion without

additional logic

◆

Counter enable and reset features

Full synchronous operation on both ports

– 4ns setup to clock and 1ns hold on all control, data, and

address inputs

– Data input, address, and control registers

– Fast 9ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

– 15ns cycle time, 67MHz operation in Pipelined output mode

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

TTL- compatible, single 5V (±10%) power supply

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

Available in a 100-pin Thin Quad Flatpack (TQFP) package

Green parts available. See ordering information

Functional Block Diagram

R/W

0/1

R/W

FT/PIPE

I/O

15L

I/O

-I/O

0/1

1b 0b b a 1a 0a

0a 1a

b 0b 1b

0/1

FT/PIPE

I/O

-I/O

15R

I/O

Control

I/O

Control

I/O

-I/O

14L

(1)

CLK

ADS

CNTEN

CNTRST

Counter/

Address

Reg.

MEMORY

ARRAY

Counter/

Address

Reg.

14R

(1)

CLK

ADS

CNTEN

CNTRST

3243 drw 01

NOTE:

1. A

14X

is a NC for IDT709269.

FEBRUARY 2018

DSC-3243/16

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