DM7473N datasheet, PDF - EEWORLD Datasheet

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DM7473N: DescriptionJ-K Flip-Flop, TTL/H/L Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDIP14, 0.300 INCH, PLASTIC, MS-001, DIP-14; Categorylogic; File Size42KB，3 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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DM7473N Overview

J-K Flip-Flop, TTL/H/L Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDIP14, 0.300 INCH, PLASTIC, MS-001, DIP-14

DM7473N Parametric

Parameter Name	Attribute value
Maker	Rochester Electronics
package instruction	DIP,
Reach Compliance Code	unknown
Is Samacsys	N
series	TTL/H/L
JESD-30 code	R-PDIP-T14
length	19.18 mm
Logic integrated circuit type	J-K FLIP-FLOP
Number of digits	2
Number of functions	2
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
propagation delay (tpd)	40 ns
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Trigger type	NEGATIVE EDGE
width	7.62 mm
minfmax	15 MHz
Base Number Matches	1

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DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

September 1986

Revised July 2001

DM7473

Dual Master-Slave J-K Flip-Flops

with Clear and Complementary Outputs

General Description

This device contains two independent positive pulse trig-

gered J-K flip-flops with complementary outputs. The J and

K data is processed by the flip-flops after a complete clock

pulse. While the clock is LOW the slave is isolated from the

master. On the positive transition of the clock, the data

from the J and K inputs is transferred to the master. While

the clock is HIGH the J and K inputs are disabled. On the

negative transition of the clock, the data from the master is

transferred to the slave. The logic states of the J and K

inputs must not be allowed to change while the clock is

HIGH. Data transfers to the outputs on the falling edge of

the clock pulse. A LOW logic level on the clear input will

reset the outputs regardless of the logic states of the other

inputs.

Ordering Code:

Order Number

DM7473N

Package Number

N14A

Package Description

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Connection Diagram

Function Table

Inputs

CLR

CLK

Toggle

Outputs

HIGH Logic Level

LOW Logic Level

Either LOW or HIGH Logic Level

Positive pulse data. the J and K inputs must be held constant while

the clock is HIGH. Data is transferred to the outputs on the falling

edge of the clock pulse.

The output logic level before the indicated input conditions were

established.

Toggle

Each output changes to the complement of its previous level on

each HIGH level clock pulse.

DS006525

www.fairchildsemi.com

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