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DM74LS165 8-Bit Parallel In/Serial Output Shift Registers
August 1986
Revised March 2000
DM74LS165
8-Bit Parallel In/Serial Output Shift Registers
General Description
This device is an 8-bit serial shift register which shifts data
in the direction of Q
A
toward Q
H
when clocked. Parallel-in
access is made available by eight individual direct data
inputs, which are enabled by a low level at the shift/load
input. These registers also feature gated clock inputs and
complementary outputs from the eighth bit.
Clocking is accomplished through a 2-input NOR gate, per-
mitting one input to be used as a clock-inhibit function.
Holding either of the clock inputs HIGH inhibits clocking,
and holding either clock input LOW with the load input
HIGH enables the other clock input. The clock-inhibit input
should be changed to the high level only while the clock
input is HIGH. Parallel loading is inhibited as long as the
load input is HIGH. Data at the parallel inputs are loaded
directly into the register on a HIGH-to-LOW transition of the
shift/load input, regardless of the logic levels on the clock,
clock inhibit, or serial inputs.
Features
s
Complementary outputs
s
Direct overriding (data) inputs
s
Gated clock inputs
s
Parallel-to-serial data conversion
s
Typical frequency 35 MHz
s
Typical power dissipation 105 mW
Ordering Code:
Order Number
DM74LS165M
DM74LS165WM
DM74LS165N
Package Number
M16A
M16B
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Load Inhibit
L
H
H
H
H
X
L
L
L
H
X
L
↑
↑
X
X
X
H
L
X
A...H
a...h
X
X
X
X
Internal
Q
A
a
H
L
Q
B
b
Q
An
Q
An
Q
H
h
Q
H0
Q
Gn
Q
Gn
Q
H0
Shift/ Clock Clock Serial Parallel Outputs Output
Q
A0
Q
B0
Q
A0
Q
B0
H
=
HIGH Level (steady state)
L
=
LOW Level (steady state)
X
=
Don't Care (any input, including transitions)
↑ =
Transition from LOW-to-HIGH level
a...h
=
The level of steady-state input at inputs A through H, respectively.
Q
A0
, Q
B0
, Q
H0
=
The level of Q
A
, Q
B
, or Q
H
, respectively, before the
indicated steady-state input conditions were established.
Q
An
, Q
Gn
=
The level of Q
A
or Q
G
, respectively, before the most recent
↑
transition of the clock.
© 2000 Fairchild Semiconductor Corporation
DS006399
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DM74LS165
Logic Diagram
Timing Diagram
Typical Shift, Load, and Inhibit Sequences
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2
DM74LS165
Absolute Maximum Ratings
(Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
7V
7V
0°C to
+70°C
−65°C
to
+150°C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
f
CLK
f
CLK
t
W
t
SU
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency (Note 2)
Clock Frequency (Note 3)
Pulse Width
(Note 3)
Setup Time
(Note 4)
Clock
Load
Parallel
Serial
Enable
Shift
t
H
T
A
Hold Time (Note 4)
Free Air Operating Temperature
0
0
25
15
10
20
30
45
0
0
70
ns
°C
ns
Parameter
Min
4.75
2
0.8
−0.4
8
25
20
Nom
5
Max
5.25
Units
V
V
V
mA
mA
MHz
MHz
ns
Note 2:
C
L
=
15 pF, R
L
=
2 kΩ, T
A
=
25°C and V
CC
=
5V
Note 3:
C
L
=
50 pF, R
L
=
2 kΩ, T
A
=
25°C and V
CC
=
5V
Note 4:
T
A
=
25°C and V
CC
=
5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
V
OH
V
OL
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
I
I
I
IH
I
IL
I
OS
I
CC
Input Current @ Max
Input Voltage
HIGH Level
Input Current
LOW Level
Input Current
Short Circuit Output Current
Supply Current
V
CC
=
Max
V
I
=
2.7V
V
CC
=
Max
V
I
=
0.4V
V
CC
=
Max (Note 6)
V
CC
=
Max (Note 7)
Conditions
V
CC
=
Min, I
I
= −18
mA
V
CC
=
Min, I
OH
=
Max
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=
Max
V
IL
=
Max, V
IH
=
Min
I
OL
=
4 mA, V
CC
=
Min
V
CC
=
Max, V
I
=
7V
Shift/Load
Others
Shift/Load
Others
Shift/Load
Others
−20
21
0.35
0.25
2.7
3.4
0.4
0.5
0.4
0.3
0.1
60
20
−1.2
−0.4
−100
36
mA
µA
mA
mA
mA
V
Min
Typ
(Note 5)
Max
−1.5
Units
V
V
Note 5:
All typicals are at V
CC
=
5V, T
A
=
25° C.
Note 6:
Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 7:
With all outputs OPEN, clock inhibit and shift/load at 4.5V, and a clock pulse applied to the CLOCK input, I
CC
is measured first with the parallel inputs
at 4.5V, then again grounded.
3
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DM74LS165
Switching Characteristics
at V
CC
=
5V and T
A
=
25°C
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Load to Any Q
Load to Any Q
Clock to Any Q
Clock to Any Q
H to Q
H
H to Q
H
H to Q
H
H to Q
H
From (Input)
To (Output)
C
L
=
15 pF
Min
25
35
35
40
40
25
30
Max
R
L
=
2 kΩ, C
L
=
50 pF
Min
20
37
42
42
47
27
37
Max
Units
MHz
ns
ns
ns
ns
ns
ns
30
32
ns
25
32
ns
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