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MK1575-01GLF

Description
TSSOP-16, Tube
Categorylogic   
File Size296KB,15 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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MK1575-01GLF Overview

TSSOP-16, Tube

MK1575-01GLF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts16
Manufacturer packaging codePGG16
Reach Compliance Codecompliant
Is SamacsysN
series1575
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length5 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times2
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
minfmax80 MHz
Base Number Matches1
DATASHEET
CLOCK RECOVERY PLL
Description
The MK1575-01 is a clock recovery Phase-Locked Loop
(PLL) designed for clock synthesis and synchronization in
cost sensitive applications. The device is optimized to
accept a low-frequency reference clock to generate a
high-frequency data or graphics pixel clock. External loop
filter components allow tailoring of loop frequency response
characteristics. For low jitter / phase noise requirements
refer to the MK2069 products.
MK1575-01
Pre-Configured Input/Output
Frequency Combinations:
Telecom T/E Clock Modes (rising edge aligned):
Addr
FS2:0
000
001
010
011
Input
Clock
8 kHz
8 kHz
8 kHz
8 kHz
Output Clocks
(MHz)
CLK1
CLK2
3.088
16.384
34.368
44.736
1.544
2.048
17.184
22.368
Clock
Type
T1
E1
E3
T3
Features
Long-term output jitter <2 nsec over 10
μsec
period
External PLL clock feedback path enable “zero delay” I/O
clock skew configuration
Selectable internal feedback divider provides popular
telecom and video clock frequencies (see tables below)
Can optionally use external feedback divider to generate
other output frequencies.
Single 3.3 V supply, low-power CMOS
Power-down mode and output tri-state (pin OE)
Packaged in 16-pin TSSOP
Pb (lead) free package
Industrial temperature range available
Video Clock Modes (falling edge aligned):
Addr Input
FS2:0 Clock
(kHz)
100
101
110
111
15.625
15.734
15.625
15.734
Output Clocks
(MHz)
CLK1 CLK2
54
54
35.468
28.636
27
27
17.734
14.318
Clock
Type
PAL 601
NTSC 601
PAL 4xf
sc
NTSC 4xf
sc
Block Diagram
The standard external clock feedback configuration is shown. Use this configuration for the pre-configured input/output
frequency combinations listed above.
C
S
C
B
R
S
CHGP
Phase Charge
Detector Pump
CHPR
Clock Input
REFIN
0
MUX
1
VCO
300 pF
VS
Divider
CLK2
Divider
CLK1
CLK2
FBIN
0
MUX
1
Divider
LUT
FCLK
Divider
FCLK
3
FS2:0
External Feedback Clock Connection
OE
IDT™
CLOCK RECOVERY PLL
1
MK1575-01
REV P 051310

MK1575-01GLF Related Products

MK1575-01GLF MK1575-01GILF MK1575-01GILFTR MK1575-01GLFTR
Description TSSOP-16, Tube TSSOP-16, Tube TSSOP-16, Reel TSSOP-16, Reel
Brand Name Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free Lead free Lead free
Is it Rohs certified? conform to conform to conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP TSSOP TSSOP
package instruction TSSOP, TSSOP, TSSOP, TSSOP,
Contacts 16 16 16 16
Manufacturer packaging code PGG16 PGG16 PGG16 PGG16
Reach Compliance Code compliant compliant compliant compliant
series 1575 1575 1575 1575
Input adjustment DIFFERENTIAL MUX DIFFERENTIAL MUX DIFFERENTIAL MUX DIFFERENTIAL MUX
JESD-30 code R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
JESD-609 code e3 e3 e3 e3
length 5 mm 5 mm 5 mm 5 mm
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
Humidity sensitivity level 1 1 1 1
Number of functions 1 1 1 1
Number of terminals 16 16 16 16
Actual output times 2 2 2 2
Maximum operating temperature 70 °C 85 °C 85 °C 70 °C
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP TSSOP TSSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260 260 260
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm 1.2 mm 1.2 mm
Maximum supply voltage (Vsup) 3.45 V 3.45 V 3.45 V 3.45 V
Minimum supply voltage (Vsup) 3.15 V 3.15 V 3.15 V 3.15 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES
technology CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL INDUSTRIAL INDUSTRIAL COMMERCIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm 0.65 mm 0.65 mm
Terminal location DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 4.4 mm 4.4 mm 4.4 mm 4.4 mm
minfmax 80 MHz 80 MHz 80 MHz 80 MHz
Base Number Matches 1 1 1 1
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