MC88LV915TFN datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> MC88LV915TFN

MC88LV915TFN: DescriptionPLL Based Clock Driver, 88LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28; Categorylogic; File Size460KB，11 Pages; ManufacturerIDT (Integrated Device Technology)

Download Datasheet Parametric View All

MC88LV915TFN Overview

PLL Based Clock Driver, 88LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28

MC88LV915TFN Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QLCC
package instruction	PLASTIC, LCC-28
Contacts	28
Reach Compliance Code	not_compliant
Is Samacsys	N
series	88LV
Input adjustment	MUX
JESD-30 code	S-PQCC-J28
JESD-609 code	e0
length	11.505 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs	1
Number of terminals	28
Actual output times	7
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	220
power supply	3.3 V
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.75 ns
Maximum seat height	4.57 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	11.505 mm
minfmax	100 MHz
Base Number Matches	1

Preview

Download Datasheet

View All

Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order Number: MC88LV915T/D

Rev 3, 08/2001

DATA SHEET

Low Voltage Low Skew CMOS PLL

CMOS

Low Voltage Low Skew

Clock Driver, 3-State

MC88LV915T

PLL Clock Driver, 3-State

MC88LV915T

Freescale Semiconductor, Inc...

The MC88LV915T Clock Driver utilizes phase–locked loop technology to

lock its low skew outputs’ frequency and phase onto an input reference

clock. It is designed to provide clock distribution for high performance PC’s

and workstations.

The PLL allows the high current, low skew outputs to lock onto a single

clock input and distribute it with essentially zero delay to multiple

components on a board. The PLL also allows the MC88LV915T to multiply

a low frequency input clock and distribute it locally at a higher (2X) system

frequency. Multiple 88LV915’s can lock onto a single reference clock, which

is ideal for applications when a central system clock must be distributed

synchronously to multiple boards (see Figure 4 on Page 9).

LOW SKEW CMOS

PLL CLOCK DRIVER

Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180°

phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q”

frequency.

The VCO is designed to run optimally between 20 MHz and the 2X_Q F

max

specification. The wiring diagrams in Figure 2 detail

the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the

“Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.

The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1

and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on

page 2). In most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding

FREQ_SEL low (÷2) will allow the VCO to run in its optimal range (>20MHz).

In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the

88LV915T in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low

frequency board test environment. The second SYNC input can be used as a test clock input to further simplify board–level testing

(see detailed description on page 11).

Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5 and Q/2 into a high impedance state (3–state). After the

OE/RST pin goes back high Q0–Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC

input. Assuming PLL_EN is low, the outputs will remain reset until the 88LV915 sees a SYNC input pulse.

A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will go

low if phase–lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88LV915 sees

a SYNC signal and full 5V V

•

Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input

•

The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the t

specification, which defines the part–to–part skew)

•

Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available

•

Input frequency range from 5MHz – 2X_Q FMAX spec.

•

Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available

•

All outputs have

±36

mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are

TTL–level compatible.

±88mA

specifications guarantee 50Ω transmission line switching on the incident edge

•

Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.

All outputs can go into high impedance (3–state) for board test purposes

•

Lock Indicator (LOCK) accuracy indicates a phase–locked state

Yield Surface Modeling and YSM are trademarks of Motorola, Inc.

Features

Motorola, Inc. 2001

IDT™

Low Voltage Low Skew CMOS PLL Clock Driver, 3-State

For More Information On This Product,

Go to: www.freescale.com

MC88LV915T

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

Recommended Resources

CR1 series soft starter has no contactor but an intermediate relay circuit

Gantry milling machine AC feed control chart

Asynchronous pulse synthesis circuit

Low power temperature transmitter circuit

Positive regulator with NPN and PNP boost circuit

Broadband voltage follower circuit

[EEWORLD takes you DIY] Digital Oscilloscope V2.0 Progress Post (Updated on August 9): Thanks to Altera for providing the debugging development board for DIY Oscilloscope V2.0 The first version of the oscilloscope used the ARM+CPLD+FIFO+AD architecture. Since the design was an amateur D...; EEWORLD社区 DIY/Open Source Hardware

How to eliminate the oscillation when mosfet is turned on and off: Can anyone tell me how to eliminate the oscillation when the mosfet is turned on and off? Thank you....; xiaoxia Power technology

Please help me see, STM32 SPI FLASH uses DMA, is it useful to just initialize DMA and enable DMA?: The program is as follows. I initialized DMA. In the main function, I am not sure whether to add SPI_FLASH_BufferWrite(Tx_Buffer, FLASH_WriteAddress, BufferSize); if I don't add it, nothing will show ...; 墨染卿卿 stm32/stm8

About electromagnetic shielding: [size=4] As people's understanding of the harmfulness of electromagnetic leakage emission of confidential information fragments gradually deepens, various means of preventing electromagnetic leakage e...; qwqwqw2088 Analogue and Mixed Signal

I'm sick, I have a cold: I woke up from a nap yesterday and felt uncomfortable in my throat. It didn't get better today. I still have a runny nose. I have a cold. I'd better go to bed early....; wangfuchong Talking

The problem of using the application as a shell.: I want to replace explorer.exe with a dialog box Program1 as the desktop. Because I have another program running Program2. After restarting, how can I make sure that the active window is Program2 inst...; lzscws Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components