M4A5-32/32-12VNC datasheet, PDF

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M4A5-32/32-12VNC: DescriptionEE PLD, 12ns, CMOS, PQFP44, TQFP-44; CategoryProgrammable logic Programmable logic devices; File Size3MB，62 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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M4A5-32/32-12VNC Overview

EE PLD, 12ns, CMOS, PQFP44, TQFP-44

M4A5-32/32-12VNC Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Lattice
Parts packaging code	QFP
package instruction	QFP,
Contacts	44
Reach Compliance Code	compliant
ECCN code	EAR99
Is Samacsys	N
maximum clock frequency	52.6 MHz
JESD-30 code	S-PQFP-G44
JESD-609 code	e3
length	10 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	32
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	260
Programmable logic type	EE PLD
propagation delay	12 ns
Certification status	Not Qualified
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	10 mm
Base Number Matches	1

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MACH 4 CPLD Family

High Performance EE CMOS

Programmable Logic

FEATURES

High-performance, EE CMOS 3.3-V & 5-V CPLD families

Flexible architecture for rapid logic designs

MAC nclude

Adv

anc 4A Fam

e In

form ily

atio

— Excellent First-Time-Fit

and reﬁt feature

— SpeedLocking

performance for guaranteed ﬁxed timing

— Central, input and output switch matrices for 100% routability and 100% pin-out retention

High speed

— 5.0ns t

Commercial and 7.5ns t

Industrial

— 182MHz f

CNT

32 to 512 macrocells; 32 to 768 registers

44 to 352 pins in PLCC, PQFP, TQFP, BGA, or fpBGA packages

Advanced capabilities for easy system integration

— 3.3-V & 5-V JEDEC-compliant operations

— JTAG (IEEE 1149.1) compliant for boundary scan testing

— 3.3-V & 5-V JTAG in-system programming

— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)

— Safe for mixed supply voltage system designs

— Programmable pull-up or Bus-Friendly

inputs and I/Os

— Hot-socketing

— Programmable security bit

— Individual output slew rate control

Flexible architecture for a wide range of design styles

— D/T registers and latches

— Synchronous or asynchronous mode

— Dedicated input registers

— Programmable polarity

— Reset/ preset swapping

Advanced EE CMOS process provides high-performance, cost-effective solutions

Supported by Vantis DesignDirect

software for rapid logic development

— Supports HDL design methodologies with results optimized for Vantis

— Flexibility to adapt to user requirements

— Software partnerships that ensure customer success

Lattice/Vantis and third-party hardware programming support

— Lattice/VantisPRO

(formerly known as MACHPRO

) software for in-system programmability

support on PCs and automated test equipment

— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,

and System General

Publication#

17466

Amendment/0

Rev:

Issue Date:

May 1999

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