Intel386™ CXSA
EMBEDDED MICROPROCESSOR
n
Static Intel386™ CPU Core
— Low Power Consumption
— Operating Power Supply
4.5V to 5.5V - 25 and 33 MHz
4.75V to 5.25V - 40 MHz
— Operating Frequency
SA-40 = 40 MHz
SA-33 = 33 MHz
SA-25 = 25 MHz
Transparent Power-management System
Architecture
— Intel System Management Mode
Architecture Extension for Truly
Compatible Systems
— Power Management Transparent to
Operating Systems and Application
Programs
— Programmable Power-management
Modes
Clock Freeze Mode Allows Clock
Stopping at Any Time
Full 32-bit Internal Architecture
— 8-, 16-, 32-bit Data Types
— 8 General Purpose 32-bit Registers
Runs Intel386 Architecture Software in a
Cost-effective, 16-bit Hardware
Environment
— Runs Same Applications and
Operating Systems as the Intel386 SX
and Intel386 DX Processors
n
n
n
n
n
n
n
n
n
n
n
n
n
— Object Code Compatible with 8086,
80186, 80286, and Intel386 Processors
High-performance 16-bit Data Bus
— Two-clock Bus Cycles
— Address Pipelining Allows Use of
Slower, Inexpensive Memories
Integrated Memory Management Unit
(MMU)
— Virtual Memory Support
— Optional On-chip Paging
— 4 Levels of Hardware-enforced
Protection
— MMU Fully Compatible with Those of
the 80286 and Intel386 DX Processors
Virtual 8086 Mode Allows Execution of
8086 Software in a Protected and Paged
System
Large, Uniform Address Space
— 64 Megabyte Physical
— 64 Terabyte Virtual
— 4 Gigabyte Maximum Segment Size
Numerics Support with Intel387™ SX
and Intel387 SL Math Coprocessors
On-chip Debugging Support Including
Breakpoint Registers
Complete System Development Support
High-speed CHMOS Technology
100-pin Plastic Quad Flatpack Package
The Intel386™ CXSA embedded microprocessor is a 5-volt, 32-bit, fully static CPU with a 16-bit external data
bus, a 26-bit external address bus, and Intel’s System Management Mode (SMM). The Intel386 CXSA CPU
brings the vast software library of the Intel386 architecture to embedded systems. It provides the performance
benefits of 32-bit programming with the cost savings associated with 16-bit hardware systems.
The Intel386 CXSA microprocessor is manufactured on Intel’s 0.8-micron CHMOS V process. This process
provides high performance and low power consumption for power-sensitive applications. Figure 3 and Figure
4 illustrate the flexibility of low power devices with respect to temperature and frequency relationships.
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringe-
ment of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such
products. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1994
September 1994
Order Number:
272418-003
Intel386™ CXSA EMBEDDED MICROPROCESSOR
2.0
PIN DESCRIPTIONS
Table 2 lists the Intel386 CXSA microprocessor pin descriptions. The following definitions are used in the pin
descriptions:
#
I
O
I/O
P
G
The named signal is active low.
Input signal.
Output signal.
Input and output signal.
Power pin.
Ground pin.
Table 2. Pin Descriptions
Symbol
A20M#
(Note 1)
Type
I
Pin
45
Name and Function
Address 20 Mask
controls the A20 address signal. When
A20M# is low, the CPU masks off (forces low) the internal A20
physical address signal. This enables the CPU to run software
that was developed using the 8086 address “wraparound”
techniques. When A20M# is high, A20 is available on the
address bus. While the bus is floating, A20M# has no effect
on the A20 address signal. A20M# should be deasserted dur-
ing SMM if the SMM handler accesses more than 1 Mbyte of
memory.
Address Bus
outputs physical memory or port I/O addresses.
A25:1
(Note 2)
O
47–46, 80–79,
76–72, 70, 66-
64, 62–58,
56–51, 18
16
ADS#
O
Address Status
indicates that the processor is driving a valid
bus-cycle definition and address onto its pins (W/R#, D/C#,
M/IO#, BHE#, BLE#, and A25:1).
Byte High Enable
indicates that the processor is transferring
a high data byte.
Byte Low Enable
indicates that the processor is transferring
a low data byte.
Busy
indicates that the math coprocessor is busy.
CLK2
provides the fundamental timing for the device.
Data/Control
indicates whether the current bus cycle is a
data cycle (memory or I/O) or a control cycle (interrupt
acknowledge, halt, or code fetch). When D/C# is high, the bus
cycle is a data cycle; when D/C# is low, the bus cycle is a con-
trol cycle.
Data Bus
inputs data during memory read, I/O read, and
interrupt acknowledge cycles and outputs data during mem-
ory and I/O write cycles.
BHE#
BLE#
BUSY#
CLK2
D/C#
O
O
I
I
O
19
17
34
15
24
D15:0
I/O
81–83, 86–90,
92–96, 99–100,
1
NOTES:
1. This pin supports the additional features of the Intel386 CXSA microprocessor; it is not present on the Intel386 SXSA microprocessor.
2. The A25:24 pins support the additional features of the Intel386 CXSA microprocessor; they are not present on the Intel386 SXSA micro-
processor.
5
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