Features
•
Comprehensive Library of Standard Logic and I/O Cells
•
ATC18 Core and I/O Cells Designed to Operate with VDD = 1.8V ± 0.15V as Main Target
•
•
•
•
Operating Conditions
IO25 and IO33 Pad Libraries Provide Interfaces to 2.5V and 3V Environments
Oscillators Provide Stable Clock Sources
Basic Analog Input/Output, Power, Ground and Multiplexer Cells Available
General-purpose Analog Cells Include Regulators, Power Management Cells, Op
Amps, Comparators, ADCs and DACs, High-performance Analog Cells Can Be
Developed on Request
Memory Cells Compiled to the Precise Requirements of the Design
Compatible with Atmel’s Extensive Range of Microcontroller, DSP, Standard-interface
and Application-specific Cells
Cell-based ASIC
ATC18
Summary
•
•
1. Description
The Atmel ATC18 Library is fabricated on a proprietary 0.18 micron, up to six-layer-
metal CMOS process intended for use with a supply voltage of 1.8V ± 0.15V.
Table 1-
1
shows the range for which Atmel library cells have been characterized.
Table 1-1.
Symbol
V
DD
V
DD2.5
V
DD3.3
V
I
V
O
TEMP
TSG
Recommended Operating Conditions
Parameter
DC Supply Voltage
DC Supply voltage
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Free Air
Temperature Range
Storage Temperature
Industrial
Conditions
Core and Standard I/Os
2.5V Interface I/Os
3.3V Interface I/Os
Min
1.65
2.25
3
0
0
-40
-60
Typ
1.8
2.5
3.3
Max
1.95
2.75
3.6
V
DD
V
DD
+85
+150
Unit
V
V
V
V
V
°
C
°
C
NOTE:
This is a summary document.
The complete document is available
under NDA. For more information,
please contact your local Atmel sales
office.
1389CS–CASIC–06-Nov-06
1.1
Absolute Maximum Ratings
Operation of a device outside the range given in
Table 1-2
may cause permanent damage to the
device and/or affect reliability.
Table 1-2.
Symbol
V
DD
V
DD2.5
V
DD3.3
V
I
V
I
V
O
V
O
TEMP
TSG
Absolute Maximum Ratings
Parameter
DC Supply Voltage
DC Supply voltage
DC Supply Voltage
DC Input Voltage,1.8V I/Os
DC Input Voltage, 3.3V I/Os
DC Output Voltage, 1.8V I/Os
DC Output Voltage, 3.3V I/Os
Operating Free Air Temperature
Range
Storage Temperature
Industrial
Conditions
Core
2.5V Interface I/Os
3.3V Interface I/Os
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-40
-60
Max
2.0
4.0
4.0
V
DD
+ 0.3, 2.0 max
V
DD3.3
+ 0.3, 4.0 max
V
DD
+ 0.3, 2.0 max
V
DD3.3
+ 0.3, 4.0 max
+125
+150
Unit
V
V
V
V
V
V
V
°
C
°
C
The Atmel cell libraries have been designed in order to be compatible with each other. Simula-
tion representations exist for three types of operating conditions. They correspond to the
characterization conditions defined as follows:
• MIN conditions (industrial best case):
T
J
= -40° C
V
DD
(cell) = 1.95V
Process = fast
• TYP conditions (industrial typical case):
T
J
= +25° C
V
DD
(cell) = 1.8V
Process = typ
• MAX conditions (industrial worst case):
T
J
= +100° C
V
DD
(cell) = 1.60V
Process = slow
Delays to tristate are defined as delay to turn off (VGS < VT) of the driving devices.
Output pad drain current corresponds to the output current of the pad when the output voltage is
V
OL
or V
OH
. The output resistor of the pad and the voltage drop due to access resistors (in and
out of the die) are taken into account. In order to have accurate timing estimates, all character-
ization has been run on electrical netlists extracted from the layout database.
2
ATC18 Summary
1389CS–CASIC–06-Nov-06
ATC18 Summary
2. Standard Cell Library SClib
The Atmel Standard Cell Library, SClib, contains a comprehensive set of combinational logic
and storage cells. The SClib library includes cells which belong to the following categories:
• Buffers and Gates
• Multiplexers
• Flip-flops
• Scan Flip-flops
• Latches
• Adders and Subtractors
2.1
Decoding the Cell Name
Table 2-1
shows the naming conventions for the cells in the SClib library. Each cell name begins
with either a two-, three-, or four-letter code that defines the type of cell. This indicates the range
of standard cells available.
Table 2-1.
Code
AD
AH
AS
AN
AOI
AON
AOR
BH
BUFB
BUFF
BUFT
CG
CLK2
DE
DF
INV0
Cell Codes
Description
Adder
Half Adder
Adder/Subtractor
AND Gate
AND-OR-Invert Gate
AND-OR-AND-Invert Gates
AND-OR Gate
Bus Holder
Balanced Buffer
Non-Inverting Buffer
Non-Inverting 3-State Buffer
Carry Generator
Clock Buffer
D-Enabled Flip-Flop
D Flip-Flop
Inverter
Code
INVB
INVT
LA
MI
MX
ND
NR
OAI
OAN
OR
ORA
SD
SE
SU
XN
XR
Description
Balanced Inverter
Inverting 3-State Buffer
D Latch
Inverting Multiplexer
Multiplexer
NAND Gate
NOR Gate
OR-AND-Invert Gate
OR-AND-OR-Invert Gates
OR Gate
OR-AND Gate
Multiplexed Scan D Flip-Flop
Multiplexed Scan Enable D Flip-Flop
Subtractor
Exclusive NOR Gate
Exclusive OR Gate
3
1389CS–CASIC–06-Nov-06
2.2
Cell Matrices
Table 2-2
and
Table 2-3
show storage elements in the SClib library. Note that all storage ele-
ments feature buffered clock inputs and buffered output.
Table 2-2.
Macro Name
DFBRBx
DFCRBx
DFCRQx
DFCRNx
DFNRBx
DFNRQx
DFPRBx
DEPRQx
DECRQx
DENRQx
DENRBx
∞
∞
∞
∞
∞
∞
∞
D Flip-Flops
Set
∞
Clear
∞
∞
•
•
Enabled D
Input
1 x Drive
∞
∞
•
•
∞
∞
∞
∞
∞
∞
∞
2 x Drive
∞
∞
•
•
∞
∞
∞
•
∞
∞
∞
∞
∞
∞
∞
•
Single
Output
Table 2-3.
Macro Name
SDBRBx
SDCRBx
SDCRNx
SDCRQx
SDNRBx
SDNRNx
SDNRQx
SDPRBx
SECRQx
SENRQx
SEPRQx
Scan Flip-flops
Set
•
Clear
•
•
•
•
1xDrive
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2xDrive
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single
Output
4
ATC18 Summary
1389CS–CASIC–06-Nov-06
ATC18 Summary
3. Input/Output Pad Cell Libraries IO18lib, IO25lib and IO33lib
The Atmel Input/Output Cell Library IO18lib contains a comprehensive list of input, output, bi-
directional and tristate cells. The ATC18 (1.8V) cell library includes a special set of I/O cells,
IO25lib (IO33lib), for interfacing with external 2.5V (3.3V) devices.
3.1
Voltage Levels
The IO18lib library is made up exclusively of low-voltage chip interface circuits powered by a
voltage level in the range of 1.65V to 1.95V. The library is compatible with SClib, 1.8-volt stan-
dard cell library.
3.2
Power and Ground Pads
Designers are strongly encouraged to provide three kinds of power pairs for the IO18lib library.
These are “AC”, “DC” and core power pairs. AC power is used by the I/O to switch its output
from one state to the other. This switching generates noise in the AC power buses on the chip.
DC power is used by the I/O to maintain its output in a steady state. The best noise performance
is achieved when the DC power buses on the chip are free of noise; you are encouraged to use
separate power pairs for AC and DC power to prevent most of the noise in the AC power buses
from reaching the DC power buses. You can use the same power pairs to supply both DC power
to the I/Os and power to the core without affecting noise performance.
Table 3-1.
Core
Vssi/gnd
•/ •
•
•
•
•/ •
•/ •
/•
•
•
•
•
VSS Power Pad Combinations
Switching I/O
VssAC
Quiet I/O
VssDC
Library Cell Name
pv18i00
pv18a00
pv18d00
pv18e00
pv18b00
pv18f00
pv18c00
Signal Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Table 3-2.
Core
Vddi/vdd
•/ •
VDD Power Pad Combinations
Switching I/O
VddAC
•
•
•
•
•
•
•
Quiet I/O
VddDC
Library Cell Name
pv18i18
pv18a18
pv18d18
pv18e18
pv18b18
pv18f18
pv18c18
Signal Name
VDD
VDD
VDD
VDD
VDD
VDD
VDD
•/ •
•/ •
/•
5
1389CS–CASIC–06-Nov-06
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