a
FEATURES
8-Bit ADC with 4 s Conversion Time
Small Footprint 8-Lead microSOIC Package
Specified Over a –40 C to +125 C Temperature Range
Inherent Track-and-Hold Functionality
Operating Supply Range: 2.7 V to 5.5 V
Specifications at 2.7 V to 5.5 V and 5 V 10%
Microcontroller Compatible Serial Interface
Optional Automatic Power-Down
Low Power Operation:
570 W at 10 kSPS Throughput Rate
2.9 mW at 50 kSPS Throughput Rate
Analog Input Range: 0 V to V
REF
Reference Input Range: 0 V to V
DD
“Drop In” Upgrade to 10 Bits Available (AD7810)
APPLICATIONS
Low Power, Hand-Held Portable Applications
Requiring Analog-to-Digital Conversion
with 8-Bit Accuracy, e.g.,
Battery-Powered Test Equipment
Battery-Powered Communications Systems
2.7 V to 5.5 V, 5 s, 8-Bit
ADC in 8-Lead microSOIC/DIP
AD7823
FUNCTIONAL BLOCK DIAGRAM
V
DD
AGND
V
REF
AD7823
CHARGE
REDISTRIBUTION
DAC
CLOCK
OSC
SERIAL
PORT
D
OUT
SCLK
V
IN+
V
IN–
COMP
V
DD
/3
CONTROL
LOGIC
CONVST
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7823 is a high speed, low power, 8-bit A/D converter
that operates from a single 2.7 V to 5.5 V supply. The part con-
tains a 4
µs
typ successive approximation A/D converter, inherent
track-and-hold functionality (with a pseudo differential input)
and a high speed serial interface that interfaces to most microcon-
trollers. The AD7823 is fully specified over a temperature range
of –40°C to +125°C.
By using a technique that samples the state of the
CONVST
(convert start) signal at the end of a conversion, the AD7823
may be used in an automatic power-down mode. When used in
this mode, the AD7823 powers down automatically at the end
of a conversion and “wakes up” at the start of a new conversion.
This feature significantly reduces the power consumption of the
part at lower throughput rates. The AD7823 can also operate in
a high speed mode where the part is not powered down between
conversions. In this high speed mode of operation, the conver-
sion time of the AD7823 is 4
µs
typ. The maximum throughput
rate is dependent on the speed of the serial interface of the
microcontroller.
The part is available in a small, 8-lead 0.3" wide, plastic dual-in-
line package (mini-DIP); in an 8-lead, small outline IC (SOIC);
and in an 8-lead microSOIC package.
1. Complete, 8-Bit ADC in 8-Lead Package
The AD7823 is an 8-bit 4
µs
typ ADC with inherent track-
and-hold functionality and a high speed serial interface—all
in an 8-lead microSOIC package. V
REF
may be connected to
V
DD
to eliminate the need for an external reference. The result
is a high speed, low power, space saving ADC solution.
2. Low Power, Single Supply Operation
The AD7823 operates from a single 2.7 V to 5.5 V supply and
typically consumes only 9 mW of power. The power dissipa-
tion can be significantly reduced at lower throughput rates by
using the automatic power-down mode, e.g., at a throughput
rate of 10 kSPS the power consumption is only 570
µW.
3. Automatic Power-Down
The automatic power-down mode, whereby the AD7823
“powers down” at the end of a conversion and “wakes up”
before the next conversion, means the AD7823 is ideal for
battery powered applications. See Power vs. Throughput
Rate section.
4. Serial Interface
An easy to use, fast serial interface allows connection to most
popular microprocessors with no external circuitry.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD7823–SPECIFICATIONS
(GND = 0 V, V
Parameter
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) Ratio
1, 2
Total Harmonic Distortion
1
Peak Harmonic or Spurious Noise
1
Intermodulation Distortion
2
2nd Order Terms
3rd Order Terms
DC ACCURACY
Resolution
Relative Accuracy
1
Differential Nonlinearity (DNL)
1
Gain Error
1
Offset Error
1
Total Unadjusted Error
1
Minimum Resolution for Which
No Missing Codes Are Guaranteed
ANALOG INPUT
Input Voltage Range
Input Leakage Current
2
Input Capacitance
2
REFERENCE INPUTS
2
V
REF
Input Voltage Range
Input Leakage Current
Input Capacitance
LOGIC INPUTS
2
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
Input Current, I
IN
Input Capacitance, C
IN
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
High Impedance Leakage Current
High Impedance Capacitance
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
1
POWER SUPPLY
V
DD
I
DD
Power Dissipation
Power-Down Mode
I
DD
Power Dissipation
Automatic Power Down
1 kSPS Throughput
10 kSPS Throughput
50 kSPS Throughput
Y Version
48
–70
–70
–77
–77
8
±
0.5
±
0.5
±
1
±
1
±
1
8
0
V
REF
±
1
15
1.2
V
DD
±
1
20
2.0
0.4
±
1
8
2.4
0.4
±
1
15
4
100
2.7–5.5
3.5
17.5
1
5
54
540
2.7
REF
= V
DD
. All specifications –40 C to +125 C unless otherwise noted.)
Unit
dB min
dB typ
dB typ
fa = 48 kHz, fb = 48.5 kHz
dB typ
dB typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
Bits
V min
V max
µA
max
pF max
V min
V max
µA
max
pF max
V min
V max
µA
max
pF max
V min
V max
µA
max
pF max
µs
typ
ns max
Volts
mA max
mW max
µA
max
µW
max
µW
max
µW
max
mW max
Test Conditions/Comments
f
IN
= 30 kHz, f
SAMPLE
= 133 kHz
Typically 10 nA, V
IN
= 0 V to V
DD
I
SOURCE
= 200
µA
I
SINK
= 200
µA
See DC Acquisition Section
For Specified Performance
Sampling at 133 kSPS and Logic
Inputs @ V
DD
or 0 V. V
DD
= 5 V
Nominal Supplies
Nominal Supplies
V
DD
= 3 V
NOTES
1
See Terminology.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
–2–
REV. C
AD7823
TIMING CHARACTERISTICS
1, 2
(–40 C to +125 C, unless otherwise noted)
Parameter
t
1
t
2
t
3
t
4
t
5 3
t
6 3
t
7 3
t
83, 4
t
POWERUP
V
DD
= 5 V
5
20
25
25
5
10
5
20
10
1.5
10%
V
DD
= 3 V
5
20
25
25
5
10
5
20
10
1.5
10%
Unit
µs
(max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
ns (max)
ns (max)
ns (min)
µs
(max)
Conditions/Comments
Conversion Time Mode 1 Operation (High Speed Mode)
CONVST
Pulsewidth
SCLK High Pulsewidth
SCLK Low Pulsewidth
CONVST
Rising Edge to SCLK Rising Edge Set-Up Time
SCLK Rising Edge to D
OUT
Data Valid Delay
Data Hold Time after Rising Edge SCLK
Bus Relinquish Time after Falling Edge of SCLK
Power-Up Time
NOTES
1
Sample tested to ensure compliance.
2
See Figures 14, 15 and 16.
3
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V
DD
= 5 V
±
10% and
0.4 V or 2 V for V
DD
= 3 V
±
10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics, t
8
, is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND
(CONVST, SCLK) . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Digital Output Voltage to GND
(D
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Analog Inputs
(V
IN+
, V
IN–
) . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 125°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 50°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . 260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 56°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
MicroSOIC Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
AD7823YN
AD7823YR
AD7823YRM
Linearity
Error
±
1 LSB
±
1 LSB
±
1 LSB
Temperature
Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Branding
Information
Package
Option*
N-8
SO-8
RM-8
C2Y
*N
= plastic DIP; RM = microSOIC; SO = small outline IC (SOIC).
I
OL
200mA
TO
OUTPUT
PIN
1.6V
C
L
50pF
I
OH
200 A
Figure 1. Load Circuit for Digital Output Timing Specifications
REV. C
–3–
AD7823
PIN FUNCTION DESCRIPTIONS
Pin No.
1
Mnemonic
CONVST
Description
Convert Start. Falling edge puts the track-and-hold into hold mode and initiates a conversion.
A rising edge on the
CONVST
pin enables the serial port of the AD7823. This is useful in
multipackage applications where a number of devices share the same serial bus. The state of
this pin at the end of conversion also determines whether the part is powered down or not.
See Operating Modes section of this data sheet.
Positive input of the pseudo differential analog input.
Negative input of the pseudo differential analog input.
Ground reference for analog and digital circuitry.
External reference is connected here.
Serial data is shifted out on this pin.
Serial Clock. An external serial clock is applied here.
Positive Supply Voltage 2.7 V to 5.5 V.
2
3
4
5
6
7
8
V
IN+
V
IN–
GND
V
REF
D
OUT
SCLK
V
DD
PIN CONFIGURATION
DIP/SOIC/microSOIC
CONVST
1
V
IN+
2
V
IN–
3
8 V
DD
AD7823
7 SCLK
TOP VIEW 6 D
OUT
(Not to Scale)
5 V
REF
GND 4
–4–
REV. C
AD7823
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is
given by:
Signal to
(Noise +
Distortion)
= (6.02N + 1.76)
dB
Thus for an 8-bit converter, this is 50 dB.
Total Harmonic Distortion
The AD7823 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second and third order terms are of different
significance. The second order terms are usually distanced in
frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
fundamental expressed in dBs.
Relative Accuracy
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7823 it is defined as:
THD
(dB)
=
20 log
V
2
+
V
3
+
V
4
+
V
5
+
V
6
V
1
2
2
2
2
2
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Offset Error
where
V
1
is the rms amplitude of the fundamental and
V
2
,
V
3
,
V
4
,
V
5
and
V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
This is the deviation of the first code transition (0000 . . . 000)
to (0000 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Gain Error
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of
the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, it
will be a noise peak.
Intermodulation Distortion
This is the deviation of the last code transition (1111 . . . 110)
to (1111 . . . 111) from the ideal (i.e., V
REF
– 1 LSB) after the
offset error has been adjusted out.
Track/Hold Acquisition Time
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa
±
nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Track/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
±
1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where there is a step input change on the input voltage applied
to the V
IN+
input of the AD7823. It means that the user must
wait for the duration of the track/hold acquisition time, after the
end of conversion or after a step input change to V
IN
, before
starting another conversion to ensure that the part operates to
specification.
Typical Performance Characteristics
10
0
–10
–20
AD7823
2048 POINT FFT
SAMPLING 136.054
f
IN
29.961
0
POWER – mW
–30
–40
dBs
–50
–60
0.1
–70
–80
–90
0.01
1
23
45
67
89
111
133
155
177
199
221
243
265
287
309
331
353
375
397
419
441
463
485
507
529
551
573
595
617
639
661
683
705
727
749
771
793
815
837
859
881
903
925
947
969
991
1013
0
10
20
30
THROUGHPUT – kSPS
40
50
–100
FREQUENCY BINS
Figure 2. Power vs. Throughput
Figure 3. AD7823 SNR
REV. C
–5–
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