Data Sheet
FEATURES
<1 pC charge injection over full signal range
1 pF off capacitance
33 V supply range
120 Ω on resistance
Fully specified at ±15 V/+12 V
3 V logic compatible inputs
Rail-to-rail operation
Break-before-make switching action
Available in a 16-lead TSSOP, a 16-lead LFCSP, and a
16-lead SOIC
Typical power consumption < 0.03 µW
Low Capacitance, 4-/8-Channel,
±15 V/+12 V
iCMOS
Multiplexers
ADG1208/ADG1209
FUNCTIONAL BLOCK DIAGRAMS
ADG1208
S1
S1A
DA
S4A
D
S1B
DB
S8
1-OF-8
DECODER
S4B
1-OF-4
DECODER
05713-001
ADG1209
APPLICATIONS
Audio and video routing
Automatic test equipment
Data-acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
A0 A1 A2 EN
A0
A1
EN
Figure 1.
GENERAL DESCRIPTION
The
ADG1208
and
ADG1209
are monolithic,
iCMOS®
analog
multiplexers comprising eight single channels and four differential
channels, respectively. The
ADG1208
switches one of eight inputs
to a common output as determined by the 3-bit binary address
lines A0, A1, and A2. The
ADG1209
switches one of four
differential inputs to a common differential output as determined
by the 2-bit binary address lines A0 and A1. An EN input on
both devices enable or disable the device. When disabled, all
channels are switched off. When on, each channel conducts
equally well in both directions and has an input signal range
that extends to the supplies.
The industrial CMOS (iCMOS) modular manufacturing
process combines high voltage complementary metal-oxide
semiconductor (CMOS) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage devices has been able to achieve. Unlike analog
ICs using conventional CMOS processes,
iCMOS
components
can tolerate high supply voltages while providing increased
performance, dramatically lower power consumption, and
reduced package size.
The ultralow capacitance and exceptionally low charge injection
of these multiplexers make them ideal solutions for data acquisition
and sample-and-hold applications, where low glitch and fast
settling are required. Figure 2 shows that there is minimum
charge injection over the entire signal range of the device.
iCMOS
construction also ensures ultralow power dissipation,
making the devices ideally suited for portable and battery-
powered instruments.
MUX (SOURCE TO DRAIN)
0.9 T
A
= 25°C
0.8
CHARGE INJECTION (pC)
1.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–15
–10
V
DD
= +5V
V
SS
= –5V
–5
0
V
S
(V)
5
10
15
05713-051
V
DD
= +15V
V
SS
= –15V
V
DD
= +12V
V
SS
= 0V
Figure 2. Source to Drain Charge Injection vs. Source Voltage
Rev. E
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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ADG1208/ADG1209
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 5
Absolute Maximum Ratings............................................................ 7
Data Sheet
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 16
Test Circuits ..................................................................................... 17
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 21
REVISION HISTORY
6/2016—Rev. D to Rev. E
Changes to Analog Inputs Parameter, Table 3 .............................. 7
Added Digital Inputs Parameter, Table 3 ...................................... 7
Moved Figure 7 ............................................................................... 10
Change to Table 7 ........................................................................... 10
Deleted Table 8; Renumbered Sequentially ................................ 11
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
3/2016—Rev. C to Rev. D
Changes to Table 4 Title ................................................................... 8
Changes to Table 5 Title ................................................................... 9
Changes to Table 7 Title ................................................................. 10
Changes to Figure 7 ........................................................................ 11
Added Table 8; Renumbered Sequentially .................................. 11
Changes to Table 9 Title ................................................................. 12
8/2015—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Added Figure 4; Renumbered Sequentially .................................. 8
Changes to Table 4 ............................................................................ 8
Changes to Figure 5 .......................................................................... 9
Added Table 5; Renumbered Sequentially .................................... 9
Added Figure 7 ................................................................................ 10
Changes to Table 7 .......................................................................... 10
Changes to Figure 8 ........................................................................ 11
Added Table 8.................................................................................. 11
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
1/2009—Rev. A to Rev. B
Change to I
DD
Parameter, Table 1 ....................................................4
Change to I
DD
Parameter, Table 2 ....................................................6
4/2007—Rev. 0 to Rev. A
Added 16-lead SOIC .......................................................... Universal
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................5
Changes to Figure 10 and Figure 11............................................. 10
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 18
4/2006—Revision 0: Initial Version
Rev. E | Page 2 of 21
Data Sheet
SPECIFICATIONS
DUAL SUPPLY
ADG1208/ADG1209
V
DD
= +15 V ± 10%, V
SS
= –15 V ± 10%, GND = 0 V, unless otherwise noted. Temperature range is as follows: Y version: –40°C to +125°C.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, R
ON
On-Resistance Match Between Channels, ∆R
ON
On-Resistance Flatness, R
FLAT
(On)
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off )
Drain Off Leakage, I
D
(Off )
ADG1208
ADG1209
Channel On Leakage, I
D
, I
S
(On)
ADG1208
ADG1209
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INL
or I
INH
Digital Input Capacitance, C
IN
DYNAMIC CHARACTERISTICS
1
Transition Time, t
TRANSITION
t
ON
(EN)
t
OFF
(EN)
Break-Before-Make Time Delay, t
BBM
Charge Injection
Off Isolation
Channel to Channel Crosstalk
Total Harmonic Distortion Plus Noise
−3 dB Bandwidth
C
S
(Off )
C
D
(Off ),
ADG1208
C
D
(Off ),
ADG1209
+25ºC
−40ºC to
+85ºC
−40ºC to
+125ºC
V
SS
to V
DD
120
200
3.5
6
20
64
±0.003
±0.1
±0.003
±0.1
±0.1
±0.02
±0.2
±0.2
240
10
76
270
12
83
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
V min
V max
µA max
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
Test Conditions/Comments
V
S
= ±10 V, I
S
= −1 mA, see Figure 31
V
DD
= +13.5 V, V
SS
= −13.5 V
V
S
= ±10 V, I
S
= −1 mA
V
S
= −5 V/0 V/+5 V, I
S
= −1 mA
V
D
= ±10 V, V
S
= −10 V, see Figure 32
V
S
= 1 V/10 V, V
D
= 10 V/1 V, see Figure 32
±0.6
±0.6
±0.6
±0.6
±0.6
±1
±1
±1
±1
±1
2.0
0.8
V
S
= V
D
= ±10 V, see Figure 33
±0.005
±0.1
2
80
130
75
95
83
100
25
0.4
−85
−85
0.15
550
1
1.5
6
7
3.5
4.5
V
IN
= V
INL
or V
INH
165
105
125
185
115
140
10
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 10 V, see Figure 34
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 10 V, see Figure 36
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 10 V, see Figure 36
R
L
= 300 Ω, C
L
= 35 pF
V
S1
= V
S2
= 10 V, see Figure 35
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF, see Figure 37
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 38
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 40
R
L
= 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz,
see Figure 41
R
L
= 50 Ω, C
L
= 5 pF, see Figure 39
f = 1 MHz, V
S
= 0 V
f = 1 MHz, V
S
= 0 V
f = 1 MHz, V
S
= 0 V
f = 1 MHz, V
S
= 0 V
f = 1 MHz, V
S
= 0 V
f = 1 MHz, V
S
= 0 V
Rev. E | Page 3 of 21
ADG1208/ADG1209
Parameter
C
D
, C
S
(On),
ADG1208
C
D
, C
S
(On),
ADG1209
POWER REQUIREMENTS
I
DD
I
DD
I
SS
I
SS
V
DD
/V
SS
1
Data Sheet
+25ºC
7
8
5
6
0.002
1.0
220
380
0.002
1.0
0.002
1.0
±5/±16.5
−40ºC to
+85ºC
−40ºC to
+125ºC
Unit
pF typ
pF max
pF typ
pF max
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
V min/max
Test Conditions/Comments
f = 1 MHz, V
S
= 0 V
f = 1 MHz, V
S
= 0 V
f = 1 MHz, V
S
= 0 V
f = 1 MHz, V
S
= 0 V
V
DD
= +16.5 V, V
SS
= −16.5 V
Digital inputs = 0 V or V
DD
Digital inputs = 5 V
Digital inputs = 0 V or V
DD
Digital inputs = 5 V
|V
DD
| = |V
SS
|
Guaranteed by design, not subject to production test.
Rev. E | Page 4 of 21
Data Sheet
SINGLE SUPPLY
ADG1208/ADG1209
V
DD
= 12 V ± 10%, V
SS
= 0 V, GND = 0 V, unless otherwise noted. Temperature range is as follows: Y version: –40°C to +125°C.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, R
ON
On-Resistance Match Between
Channels, ∆R
ON
On-Resistance Flatness, R
FLAT
(On)
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off )
Drain Off Leakage, I
D
(Off )
ADG1208
ADG1209
Channel On Leakage I
D
, I
S
(On)
ADG1208
ADG1209
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INL
or I
INH
Digital Input Capacitance, C
IN
DYNAMIC CHARACTERISTICS
1
Transition Time, t
TRANSITION
t
ON
(EN)
t
OFF
(EN)
Break-Before-Make Time Delay, t
BBM
Charge Injection
Off Isolation
Channel to Channel Crosstalk
−3 dB Bandwidth
C
S
(Off )
C
D
(Off ),
ADG1208
C
D
(Off ),
ADG1209
C
D
, C
S
(On),
ADG1208
C
D
, C
S
(On),
ADG1209
+25ºC
−40ºC to
+85ºC
−40ºC to
+125ºC
0 to V
DD
300
475
5
16
60
±0.003
±0.1
±0.003
±0.1
±0.1
±0.02
±0.2
±0.2
567
625
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
V min
V max
µA max
pF typ
ns typ
210
140
155
235
ns typ
160
ns typ
175
20
−0.2
−85
−85
450
1.2
1.8
7.5
9
4.5
5.5
9
10.5
6
7.5
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
pF typ
pF max
pF typ
pF max
V
IN
= V
INL
or V
INH
Test Conditions/Comments
V
S
= 0 V to 10 V, I
S
= −1 mA, see Figure 31
V
DD
= 10.8 V, V
SS
= 0 V
V
S
= 0 V to 10 V, I
S
= −1 mA
26
27
V
S
= 3 V/6 V/9 V, I
S
= −1 mA
V
DD
= 13.2 V
V
S
= 1 V/10 V, V
D
= 10 V/1 V, see Figure 32
V
S
= 1 V/10 V, V
D
= 10 V/1 V, see Figure 32
±0.6
±0.6
±0.6
±0.6
±0.6
±1
±1
±1
±1
±1
2.0
0.8
V
S
= V
D
= 1 V or 10 V, see Figure 33
±0.001
±0.1
3
100
170
90
110
105
130
45
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 8 V, see Figure 34
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 8 V, see Figure 36
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 8 V, see Figure 36
R
L
= 300 Ω, C
L
= 35 pF
V
S1
= V
S2
= 8 V, see Figure 35
V
S
= 6 V, R
S
= 0 Ω, C
L
= 1 nF, see Figure 37
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 38
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 40
R
L
= 50 Ω, C
L
= 5 pF, see Figure 39
f = 1 MHz, V
S
= 6 V
f = 1 MHz, V
S
= 6 V
f = 1 MHz, V
S
= 6 V
f = 1 MHz, V
S
= 6 V
f = 1 MHz, V
S
= 6 V
f = 1 MHz, V
S
= 6 V
f = 1 MHz, V
S
= 6 V
f = 1 MHz, V
S
= 6 V
f = 1 MHz, V
S
= 6 V
f = 1 MHz, V
S
= 6 V
Rev. E | Page 5 of 21
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