Addition of 16-Lead Lead Frame Chip Scale Package .. Universal
Edits to Features.................................................................................1
Edits to General Description ...........................................................1
Addition of LFCSP Pin Configuration ...........................................4
Edit to Absolute Maximum Ratings................................................4
Addition to Ordering Guide ............................................................4
Addition of CP-16 Outline Dimensions .................................... 19
2/01—Rev. 0 to Rev A
Edits to Notes in the Ordering Guide
Rev. F | Page 2 of 28
Data Sheet
SPECIFICATIONS
V
CC
= 2.7 V to 3.6 V, V
REF
= 2.5 V internal or external, f
DCLK
= 2 MHz; T
A
= −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
DC ACCURACY
Resolution
No Missing Codes
Integral Nonlinearity
2
Differential Nonlinearity
2
Offset Error
2
Gain Error
2
Noise
Power Supply Rejection
SWITCH DRIVERS
On Resistance
2
Y+, X+
Y–, X–
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE INPUT/OUTPUT
Internal Reference Voltage
Internal Reference Tempco
V
REF
Input Voltage Range
DC Leakage Current
V
REF
Input Impedance
TEMPERATURE MEASUREMENT
Temperature Range
Resolution
Differential Method
3
Single Conversion Method
4
Accuracy
Differential Method
3
Single Conversion Method
4
BATTERY MONITOR
Input Voltage Range
Input Impedance
Accuracy
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN 5
AD7873A
1
12
11
±2
±6
±4
70
70
AD7873B
1
12
12
±1
–0.9/+1.5
±6
±4
70
70
Unit
Bits
Bits min
LSB max
LSB max
LSB max
LSB max
µV rms typ
dB typ
Test Conditions/Comments
AD7873
+V
CC
= 2.7 V
External reference
5
6
0 to V
REF
±0.1
37
2.45/2.55
±15
1/V
CC
±1
1
5
6
0 to V
REF
±0.1
37
2.45/2.55
±15
1/V
CC
±1
1
Ω typ
Ω typ
V
µA typ
pF typ
V min/max
ppm/°C typ
V min/max
µA max
GΩ typ
CS = GND or +V
CC
; typically 260 Ω when the
on-board reference is enabled
–40/+85
1.6
0.3
±2
±2
0/6
10
±2.5
±3
2.4
0.4
±1
10
–40/+85
1.6
0.3
±2
±2
0/6
10
±2
±3
2.4
0.4
±1
10
°C min/max
°C typ
°C typ
°C typ
°C typ
V min/max
kΩ typ
% max
% max
V min
V max
µA max
pF max
Sampling; 1 GΩ when battery monitor is off
External reference
Internal reference
Typically 10 nA, V
IN
= 0 V or +V
CC
Rev. F | Page 3 of 28
AD7873
Parameter
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
PENIRQ Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
5
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
+V
CC
(Specified Performance)
I
CC 6
Normal Mode (f
SAMPLE
= 125 kSPS)
Normal Mode (f
SAMPLE
= 12.5 kSPS)
Normal Mode (Static)
Shutdown Mode (Static)
Power Dissipation
6
Normal Mode (f
SAMPLE
= 125 kSPS)
Shutdown
1
2
Data Sheet
AD7873A
1
V
CC
– 0.2
0.4
0.4
±10
10
AD7873B
1
Unit
Test Conditions/Comments
I
SOURCE
= 250 µA; V
CC
= 2.2 V to 5.25 V
I
SINK
= 250 µA
100 kΩ pull-up; I
SINK
= 250 µA
V
CC
– 0.2
V min
0.4
V max
0.4
V max
±10
µA max
10
pF max
Straight (Natural) Binary
12
3
125
2.7/3.6
380
670
170
150
580
1
1.368
2.412
3.6
DCLK cycles max
DCLK cycles min
kSPS max
V min/max
µA max
µA typ
µA typ
µA typ
µA typ
µA max
mW max
mW typ
µW max
Functional from 2.2 V to 5.25 V
Digital I/Ps = 0 V or V
CC
Internal reference off, V
CC
= 3.6 V, 240 µA typ
Internal reference on, V
CC
= 3.6 V
Internal reference off, V
CC
= 2.7 V, f
DCLK
= 200 kHz
Internal reference off, V
CC
= 3.6 V
Internal reference on, V
CC
= 3.6 V
200 nA typ
Internal reference off, V
CC
= 3.6 V
Internal reference on, V
CC
= 3.6 V
V
CC
= 3.6 V
12
3
125
2.7/3.6
380
670
170
150
580
1
1.368
2.412
3.6
Temperature range as follows: A, B Versions: –40°C to +85°C.
See the Terminology section.
3
Difference between TEMP0 and TEMP1 measurement. No calibration necessary.
4
Temperature drift is –2.1 mV/°C.
5
Sample tested @ 25°C to ensure compliance.
6
See the Power vs. Throughput Rate section.
Rev. F | Page 4 of 28
Data Sheet
TIMING SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, unless otherwise noted; V
CC
= 2.7 V to 5.25 V, V
REF
= 2.5 V.
Table 2. Timing Specifications
1
Parameter
f
DCLK 2
t
ACQ
t
1
t
2
t
3 3
t
4
t
5
t
6
t
7
t
8
t
93
t
10
t
11
t
12 4
1
2
AD7873
Limit at T
MIN
, T
MAX
10
2
1.5
10
60
60
200
200
60
10
10
200
0
100
100
Unit
kHz min
MHz max
µs min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
Description
Acquisition time
CS falling edge to first DCLK rising edge
CS falling edge to busy three-state disabled
CS falling edge to DOUT three-state disabled
DCLK high pulse width
DCLK low pulse width
DCLK falling edge to BUSY rising edge
Data setup time prior to DCLK rising edge
Data valid to DCLK hold time
Data access time after DCLK falling edge
CS rising edge to DCLK ignored
CS rising edge to BUSY high impedance
CS rising edge to DOUT high impedance
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.6 V.
Mark/space ratio for the DCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V.
4
t
12
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
12
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
02164-002
Figure 2. Load Circuit for Digital Output Timing Specifications
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