MicroConverter
®
Multichannel
24-/16-Bit ADCs with Embedded 62 kB
Flash and Single-Cycle MCU
Data Sheet
FEATURES
High resolution Σ-Δ ADCs
2 independent 24-bit ADCs on the ADuC845
Single 24-bit ADC on the ADuC847 and
single 16-bit ADC on the ADuC848
Up to 10 ADC input channels on all parts
24-bit no missing codes
22-bit rms (19.5 bit p-p) effective resolution
Offset drift 10 nV/°C, gain drift 0.5 ppm/°C chop enabled
Memory
62-kbyte on-chip Flash/EE program memory
4-kbyte on-chip Flash/EE data memory
Flash/EE, 100-year retention, 100 kcycle endurance
3 levels of Flash/EE program memory security
In-circuit serial download (no external hardware)
High speed user download (5 sec)
2304 bytes on-chip data RAM
8051-based core
8051-compatible instruction set
High performance single-cycle core
32 kHz external crystal
On-chip programmable PLL (12.58 MHz max)
3 × 16-bit timer/counter
24 programmable I/O lines, plus 8 analog or
digital input lines
11 interrupt sources, two priority levels
Dual data pointer, extended 11-bit stack pointer
On-chip peripherals
Internal power-on reset circuit
12-bit voltage output DAC
Dual 16-bit Σ-Δ DACs
On-chip temperature sensor (ADuC845 only)
Dual excitation current sources (200 µA)
Time interval counter (wake-up/RTC timer)
UART, SPI®, and I
2
C® serial I/O
High speed dedicated baud rate generator (incl. 115,200)
Watchdog timer (WDT)
Power supply monitor (PSM)
ADuC845/ADuC847/ADuC848
Power
Normal: 4.8 mA max @ 3.6 V (core CLK = 1.57 MHz)
Power-down: 20 µA max with wake-up timer running
Specified for 3 V and 5 V operation
Package and temperature range:
52-lead MQFP (14 mm × 14 mm), −40°C to +125°C
56-lead LFCSP (8 mm × 8 mm), −40°C to +85°C
APPLICATIONS
Multichannel sensor monitoring
Industrial/environmental instrumentation
Weigh scales, pressure sensors, temperature monitoring
Portable instrumentation, battery-powered systems
Data logging, precision system monitoring
FUNCTIONAL BLOCK DIAGRAM
AV
DD
ADuC845
AVCO
CURRENT
SOURCE
PRIMARY
24-BIT
S-D
ADC
IEXC1
IEXC2
AIN1
BUF
PGA
12-BIT
DAC
BUF
DAC
MUX
AIN10
AINCOM
AGND
AUXILIARY
24-BIT
S-D
ADC
TEMP
SENSOR
DUAL 16-BIT
S-D
DAC
MUX
DUAL 16-BIT
PWM
PWM0
PWM1
REFIN2+
REFIN2–
REFIN–
REFIN+
EXTERNAL
V
REF
DETECT
INTERNAL
BAND GAP
V
REF
SINGLE-CYCLE 8061-BASED MCU
RESET
DV
DD
DGND
POR
PLL AND PRG
CLOCK DIV
OSC
WAKE-UP/
RTC TIMER
62 kBYTES FLASH/EE PROGRAM MEMORY
4 kBYTES FLASH/EE DATA MEMORY
2304 BYTES USER RAM
3
×
16 BIT TIMERS
BAUD RATE TIMER
4
×
PARALLEL
PORTS
POWER SUPPLY MON
WATCHDOG TIMER
UART, SPI, AND I
2
C
SERIAL I/O
04741-001
XTAL1
XTAL2
Figure 1. ADuC845 Functional Block Diagram
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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ADuC845/ADuC847/ADuC848
TABLE OF CONTENTS
Specifications..................................................................................... 4
Abosolute Maximum Ratings ....................................................... 10
ESD Caution ................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
General Description ....................................................................... 15
8052 Instruction Set ................................................................... 18
Timer Operation ......................................................................... 18
ALE ............................................................................................... 18
External Memory Access ........................................................... 18
Complete SFR Map .................................................................... 19
Functional Description .................................................................. 20
8051 Instruction Set ................................................................... 20
Memory Organization ............................................................... 22
Special Function Registers (SFRs) ............................................ 24
ADC Circuit Information.......................................................... 26
Auxiliary ADC (ADuC845 Only) ............................................ 32
Reference Inputs ......................................................................... 32
Burnout Current Sources .......................................................... 32
Reference Detect Circuit ........................................................... 33
Sinc Filter Register (SF) ............................................................. 33
Σ-∆ Modulator ............................................................................ 33
Digital Filter ................................................................................ 33
ADC Chopping ........................................................................... 34
Calibration ................................................................................... 34
Programmable Gain Amplifier ................................................. 35
Bipolar/Unipolar Configuration .............................................. 35
Data Output Coding .................................................................. 36
Excitation Currents .................................................................... 36
ADC Power-On .......................................................................... 36
Typical Performance Characteristics ........................................... 37
Functional Description .................................................................. 39
Data Sheet
ADC SFR Interface..................................................................... 39
ADCSTAT (ADC Status Register) ........................................... 40
ADCMODE (ADC Mode Register)......................................... 41
ADC0CON1 (Primary ADC Control Register) ..................... 43
ADC0CON2 (Primary ADC Channel Select Register) ........ 44
SF (ADC Sinc Filter Control Register) .................................... 46
ICON (Excitation Current Sources Control Register) .......... 47
Nonvolatile Flash/EE Memory Overview ............................... 48
Flash/EE Program Memory ...................................................... 49
User Download Mode (ULOAD)............................................. 50
Using Flash/EE Data Memory .................................................. 51
Flash/EE Memory Timing ........................................................ 52
DAC Circuit Information .......................................................... 53
Pulse-Width Modulator (PWM) .............................................. 55
On-Chip PLL (PLLCON) .......................................................... 60
I
2
C Serial Interface ..................................................................... 61
SPI Serial Interface ..................................................................... 64
Using the SPI Interface .............................................................. 66
Dual Data Pointers ..................................................................... 67
Power Supply Monitor ............................................................... 68
Watchdog Timer ......................................................................... 69
Time Interval Counter (TIC) .................................................... 70
8052-Compatible On-Chip Peripherals .................................. 73
Timers/Counters ........................................................................ 75
UART Serial Interface ................................................................ 80
Interrupt System ......................................................................... 85
Interrupt Priority ........................................................................ 86
Interrupt Vectors ........................................................................ 86
Hardware Design Considerations ................................................ 87
External Memory Interface ....................................................... 87
Power Supplies ............................................................................ 87
Rev. C | Page 2 of 108
Data Sheet
Power-On Reset Operation........................................................88
Power Consumption ...................................................................88
Power-Saving Modes ..................................................................88
Grounding and Board Layout Recommendations .................89
Other Hardware Considerations ...............................................90
QuickStart Development System ..................................................94
ADuC845/ADuC847/ADuC848
QuickStart-PLUS Development System .................................. 94
Timing Specifications ..................................................................... 95
Outline Dimensions ......................................................................104
Ordering Guide .........................................................................105
REVISION HISTORY
12/12—Rev. B to Rev. C
Changes to Figure 3 and Table 3 ...................................................11
Changes to Burnout Current Sources Section.............................32
Change to ADCMODE (ADC Mode Register) Section.............42
Changes to Mode 4 (Dual NRZ 16-Bit Σ-∆ DAC) Section ............58
Change to Hardware Slave Mode Section ....................................63
Updated Outline Dimensions ......................................................104
Changes to Ordering Guide .........................................................105
2/05—Rev. A to Rev. B
Changes to Figure 1........................................................................... 1
Changes to the Burnout Current Sources Section ......................32
Changes to the Excitation Currents Section ................................36
Changes to Table 30 ........................................................................47
Changes to the Flash/EE Memory on the ADuC845, ADuC847,
ADuC848 Section......................................................................48
Changes to Figure 39 ......................................................................57
Changes to On-Chip PLL (PLLCON) Section ............................60
Added 3 V Part Section Heading ..................................................88
Added 5 V Part Section ..................................................................88
Changes to Figure 70 ......................................................................91
Changes to Figure 71 ......................................................................93
6/04—Rev. 0 to Rev. A
Changes to Figure 5.........................................................................17
Changes to Figure 6.........................................................................18
Changes to Figure 7.........................................................................19
Changes to Table 5 ..........................................................................24
Changes to Table 24 ........................................................................41
Changes to Table 25 ........................................................................ 43
Changes to Table 26 ........................................................................ 44
Changes to Table 27 ........................................................................ 45
Changes to User Download Mode Section .................................. 50
Added Figure 51 and Renumbered Subsequent Figures ............ 50
Edits to the DACH/DACL Data Registers Section ..................... 53
Changes to Table 34 ........................................................................ 56
Added SPIDAT: SPI Data Register Section ................................. 65
Changes to Table 42 ........................................................................ 67
Changes to Table 43 ........................................................................ 68
Changes to Table 44 ........................................................................ 69
Changes to Table 45 ........................................................................ 71
Changes to Table 50 ........................................................................ 75
Changes to Timer/Counter 0 and 1 Data Registers Section...... 76
Changes to Table 54 ........................................................................ 80
Added the SBUF—UART Serial Port Data Register Section..... 80
Addition to the Timer 3 Generated Baud Rates Section ........... 83
Added Table 57 and Renumbered Subsequent Tables ............... 84
Changes to Table 61 ........................................................................ 86
4/04—Revision 0: Initial Version
Rev. C | Page 3 of 108
ADuC845/ADuC847/ADuC848
SPECIFICATIONS
1
Data Sheet
AV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V, REFIN(–) = AGND; AGND =
DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz crystal; all specifications T
MIN
to T
MAX
, unless otherwise noted. Input buffer on for primary
ADC, unless otherwise noted. Core speed = 1.57 MHz (default CD = 3), unless otherwise noted.
Table 1.
Parameter
PRIMARY ADC
Conversion Rate
No Missing Codes
2
Resolution (ADuC845/ADuC847)
Resolution (ADuC848)
Output Noise (ADuC845/ADuC847)
Output Noise (ADuC848)
Integral Nonlinearity
Offset Error
3
Min
Typ
Max
Unit
Hz
Hz
Bits
Bits
Conditions
Chop on (ADCMODE.3 = 0)
Chop off (ADCMODE.3 = 1)
≤26.7 Hz update rate with chop enabled
≤80.3 Hz update rate with chop disabled
5.4
105
16.06
1365
24
24
See Table 11 and Table 15
See Table 13 and Table 17
See Table 10 and Table 14
See Table 12 and Table 16
±15
±3
μV (rms)
μV (rms)
ppm of FSR
μV
Offset Error Drift vs. Temperature
2
Full-Scale Error
4
ADuC845/ADuC847
ADuC848
Gain Error Drift vs. Temperature
4
Power Supply Rejection
80
±10
±200
±10
±10
±0.5
±0.5
nV/°C
nV/°C
μV
μV
LSB
16
ppm/°C
dB
dB
dB
Output noise varies with selected update rates,
gain range, and chop status.
Output noise varies with selected update rates,
gain range, and chop status.
1 LSB
16
Chop on
Chop off, offset error is in the order of the noise
for the programmed gain and update rate
following a calibration.
Chop on (ADCMODE.3 = 0)
Chop off (ADCMODE.3 = 1)
±20 mV to ±2.56 V
±20 mV to ±640 mV
±1.28 V to ±2.56 V
113
80
PRIMARY ADC ANALOG INPUTS
Differential Input Voltage Ranges
5, 6
Bipolar Mode (ADC0CON1.5 = 0)
Unipolar Mode (ADC0CON1.5 = 1)
ADC Range Matching
Common-Mode Rejection DC
On AIN
Common-Mode Rejection
50 Hz/60 Hz
2
On AIN
Footnotes at end of table.
AIN = 1 V, ±2.56 V, chop enabled
AIN = 7.8 mV, ±20 mV, chop enabled
AIN = 1 V, ±2.56 V, chop disabled
2
Gain = 1 to 128
V
REF
= REFIN(+) − REFIN(−) or
REFIN2(+) − REFIN2(−) (or Int 1.25 V
REF
)
V
REF
= REFIN(+) − REFIN(−) or
REFIN2(+) − REFIN2(−) (or Int 1.25 V
REF
)
AIN = 18 mV, chop enabled
Chop enabled, chop disabled
AIN = 7.8 mV, range = ±20 mV
AIN = 1 V, range = ±2.56 V
50 Hz/60 Hz ± 1 Hz, 16.6 Hz and 50 Hz update
rate, chop enabled, REJ60 enabled
AIN = 7.8 mV, range = ±20 mV
AIN = 1 V, range = ±2.56 V
±1.024 ×
V
REF
/GAIN
0 – 1.024 ×
V
REF
/GAIN
±2
95
113
V
V
μV
dB
dB
95
90
dB
dB
Rev. C | Page 4 of 108
Data Sheet
Parameter
Normal Mode Rejection 50 Hz/60 Hz
2
ADuC845/ADuC847/ADuC848
Min
75
100
67
100
Typ
Max
Unit
dB
dB
dB
dB
nA
nA
pA/°C
pA/°C
nA/V
pA/V/°C
V
V
Conditions
50 Hz/60 Hz ± 1 Hz, 16.6 Hz Fadc, SF = 52H,
chop on, REJ60 on
50 Hz ± 1 Hz, 16.6 Hz Fadc, SF = 52H, chop on
50 Hz/60 Hz ± 1 Hz, 50 Hz Fadc, SF = 52H,
chop off, REJ60 on
50 Hz ± 1 Hz, 50 Hz Fadc, SF = 52H, chop off
T
MAX
= 85°C, buffer on
T
MAX
= 125°C, buffer on
T
MAX
= 85°C, buffer on
T
MAX
= 125°C, buffer on
±2.56 V range, buffer bypassed
Buffer bypassed
AIN1…AIN10 and AINCOM with buffer enabled
AIN1…AIN10 and AINCOM with buffer bypassed
On AIN
Analog Input Current
2
±1
±5
±5
±15
±125
±2
A
GND
+
0.1
A
GND
−
0.03
2.5
1
±1
±0.1
0.3
0.65
AV
DD
AV
DD
−
0.1
AV
DD
+
0.03
Analog Input Current Drift
Average Input Current
Average Input Current Drift
Absolute AIN Voltage Limits
2
Absolute AIN Voltage Limits
2
EXTERNAL REFERENCE INPUTS
REFIN(+) to REFIN(–) Voltage
REFIN(+) to REFIN(–) Range
2
Average Reference Input Current
Average Reference Input Current
Drift
NOXREF Trigger Voltage
Common-Mode Rejection
DC Rejection
50 Hz/60 Hz Rejection
2
Normal Mode Rejection 50 Hz/60 Hz
2
V
V
µA/V
nA/V/°C
V
REFIN refers to both REFIN and REFIN2
REFIN refers to both REFIN and REFIN2
Both ADCs enabled
NOXREF (ADCSTAT.4) bit active if V
REF
> 0.3 V, and
inactive if V
REF
> 0.65 V
AIN = 1 V, range = ±2.56 V
50 Hz/60 Hz ± 1 Hz, AIN = 1 V,
range = ±2.56 V, SF = 82
50 Hz/60 Hz ±1 Hz, AIN = 1 V, range = ±2.56 V,
SF = 52H, chop on, REJ60 on
50 Hz ± 1 Hz, AIN = 1 V, range = ±2.56 V,
SF = 52H, chop on
50 Hz/60 Hz ± 1 Hz, AIN = 1 V, range = ±2.56 V,
SF = 52H, chop off, REJ60 on
50 Hz ± 1 Hz, AIN = 1 V, range = ±2.56 V,
SF = 52H, chop off
Chop on
Chop off
≤26.7 Hz update rate, chop enabled
80.3 Hz update rate, chop disabled
Output noise varies with selected update rates.
1 LSB
16
Chop on
Chop off
Chop on
Chop off
125
90
75
100
67
100
dB
dB
dB
dB
dB
dB
AUXILIARY ADC (ADuC845 Only)
Conversion Rate
No Missing Codes
2
Resolution
Output Noise
Integral Nonlinearity
Offset Error
3
Offset Error Drift
2
Full-Scale Error
4
Gain Error Drift
4
Power Supply Rejection
Footnotes at end of table.
5.4
105
16.06
1365
24
24
See Table 19 and Table 21
See Table 18 and Table 20
±15
±3
±0.25
10
200
±0.5
±0.5
80
80
Hz
Hz
Bits
Bits
ppm of FSR
µV
LSB
16
nV/°C
nV/°C
LSB
16
ppm/°C
dB
dB
AIN = 1 V, range = ±2.56 V, chop enabled
AIN = 1 V, range = ±2.56 V, chop disabled
Rev. C | Page 5 of 108
Microchip MCU
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