EEWORLDEEWORLDEEWORLD

Part Number

Search

AD680JTZ

Description
V-Ref Precision 2.5V 10mA 3-Pin TO-92 Tray
CategoryVoltage reference   
File Size381KB,12 Pages
ManufacturerADI
Websitehttps://www.analog.com
Download Datasheet Parametric Compare View All

AD680JTZ Online Shopping

Suppliers Part Number Price MOQ In stock  
AD680JTZ - - View Buy Now

AD680JTZ Overview

V-Ref Precision 2.5V 10mA 3-Pin TO-92 Tray

AD680JTZ Parametric

Parameter NameAttribute value
EU restricts the use of certain hazardous substancesCompliant
ECCN (US)EAR99
Part StatusActive
HTS8542.39.00.01
Reference TypePrecision
TopologySeries
Initial Accuracy0.4%
Maximum Temperature Coefficient30ppm/°C
Load Regulation100uV/mA
Line Regulation40uV/V
Output Voltage (V)2.5
Maximum Input Voltage (V)36
Maximum Output Current (mA)10
Minimum Operating Temperature (°C)0
Maximum Operating Temperature (°C)70
PackagingTray
Pin Count3
Standard Package NameTO-92
Supplier PackageTO-92
MountingThrough Hole
Package Height4.83
Package Length4.83
Package Width3.68
PCB changed3
Lead ShapeThrough Hole
Low Power, Low Cost
2.5 V Reference
AD680
FEATURES
Low quiescent current at 250 μA max
Laser trimmed to high accuracy
2.5 V ± 5 mV max (AN, AR grades)
Trimmed temperature coefficient
20 ppm/°C max (AN, AR grades)
Low noise at 8 μV p-p from 0.1 Hz to 10 Hz
250 nV/√Hz wideband
Temperature output pin (N, R packages)
Available in three package styles
8-lead PDIP, 8-lead SOIC, and 3-pin TO-92
CONNECTION DIAGRAMS
TP*
1
+V
IN 2
TEMP
3
GND
4
8
TP*
TP*
AD680
7
6
V
OUT
TOP VIEW
(Not to Scale)
5
NC
NC = NO CONNECT
* TP DENOTES FACTORY TEST POINT.
NO CONNECTIONS SHOULD BE MADE
TO THESE PINS.
00813-003
Figure 1. 8-Lead PDIP and 8-Lead SOIC Pin Configuration
GENERAL DESCRIPTION
The AD680 is a band gap voltage reference that provides a fixed
2.5 V output from inputs between 4.5 V and 36 V. The
architecture of the AD680 enables the reference to be operated
at a very low quiescent current while still realizing excellent dc
characteristics and noise performance. Trimming of the high
stability thin-film resistors is performed for initial accuracy and
temperature coefficient, resulting in low errors over temperature.
The precision dc characteristics of the AD680 make it ideal for
use as a reference for DACs that require an external precision
reference. The device is also ideal for ADCs and, in general, can
offer better performance than the standard on-chip references.
Based upon its low quiescent current, which rivals that of many
incomplete 2-terminal references, the AD680 is recommended
for low power applications, such as hand-held, battery-operated
equipment.
A temperature output pin is provided on the 8-lead package
versions of the AD680. The temperature output pin provides an
output voltage that varies linearly with temperature and allows
the AD680 to be configured as a temperature transducer while
providing a stable 2.5 V output.
The AD680 is available in five grades. The AD680AN is speci-
fied for operation from −40°C to +85°C, while the AD680JN is
specified for 0°C to 70°C operation. Both the AD680AN and
AD680JN are available in 8-lead PDIP packages. The AD680AR
is specified for operation from −40°C to +85°C, while the
AD680JR is specified for 0°C to 70°C operation. Both are
available in 8-lead SOIC packages. The AD680JT is specified for
0°C to 70°C operation and is available in a 3-pin TO-92
package.
AD680
BOTTOM VIEW
(Not to Scale)
3
2
1
00813-004
+V
IN
V
OUT
GND
Figure 2. Connection Diagram TO-92
PRODUCT HIGHLIGHTS
1. High Accuracy.
The AD680 band gap reference operates on a very low
quiescent current which rivals that of many 2-terminal
references. This makes the complete, higher accuracy AD680
ideal for use in power-sensitive applications.
2. Low Errors.
Laser trimming of both initial accuracy and temperature coef-
ficients results in low errors over temperature without the use
of external components. The AD680AN and AD680AR have
a maximum variation of 6.25 mV between −40°C and +85°C.
3. Low Noise.
The AD680 noise is low, typically 8 μV p-p from 0.1 Hz to
10 Hz. Spectral density is also low, typically 250 nV/√Hz.
4. Temperature Transducer.
The temperature output pin on the 8-lead package versions
enables the AD680 to be configured as a temperature
transducer.
5. Low Cost.
PDIP packaging provides machine insertability, while SOIC
packaging provides surface-mount capability. TO-92
packaging offers a cost-effective alternative to 2-terminal
references, offering a complete solution in the same package
in which 2-terminal references are usually found.
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.

AD680JTZ Related Products

AD680JTZ AD680JRZ-REEL7 AD680ARZ-REEL7 AD680ANZ AD680ARZ AD680JRZ
Description V-Ref Precision 2.5V 10mA 3-Pin TO-92 Tray V-Ref Precision 2.5V 10mA 8-Pin SOIC N T/R V-Ref Precision 2.5V 10mA 8-Pin SOIC N T/R V-Ref Precision 2.5V 10mA 8-Pin PDIP N Tube V-Ref Precision 2.5V 10mA 8-Pin SOIC N Tube V-Ref Precision 2.5V 10mA 8-Pin SOIC N Tube
EU restricts the use of certain hazardous substances Compliant Compliant Compliant Compliant Compliant Compliant
ECCN (US) EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
Part Status Active Active Active Active Active Active
HTS 8542.39.00.01 8542.39.00.01 8542.39.00.01 8542.39.00.01 8542.39.00.01 8542.39.00.01
Reference Type Precision Precision Precision Precision Precision Precision
Topology Series Series Series Series Series Series
Initial Accuracy 0.4% 0.4% 0.2% 0.2% 0.2% 0.4%
Maximum Temperature Coefficient 30ppm/°C 25ppm/°C 20ppm/°C 20ppm/°C 20ppm/°C 25ppm/°C
Load Regulation 100uV/mA 100uV/mA 100uV/mA 100uV/mA 100uV/mA 100uV/mA
Line Regulation 40uV/V 40uV/V 40uV/V 40uV/V 40uV/V 40uV/V
Output Voltage (V) 2.5 2.5 2.5 2.5 2.5 2.5
Maximum Input Voltage (V) 36 36 36 36 36 36
Maximum Output Current (mA) 10 10 10 10 10 10
Maximum Operating Temperature (°C) 70 70 85 85 85 70
Packaging Tray Tape and Reel Tape and Reel Tube Tube Tube
Pin Count 3 8 8 8 8 8
Standard Package Name TO-92 SOP SOP DIP SOP SOP
Supplier Package TO-92 SOIC N SOIC N PDIP N SOIC N SOIC N
Mounting Through Hole Surface Mount Surface Mount Through Hole Surface Mount Surface Mount
Package Height 4.83 1.5(Max) 1.5(Max) 3.3 1.5(Max) 1.5(Max)
Package Length 4.83 5(Max) 5(Max) 9.27 5(Max) 5(Max)
Package Width 3.68 4(Max) 4(Max) 6.35 4(Max) 4(Max)
PCB changed 3 8 8 8 8 8
Lead Shape Through Hole Gull-wing Gull-wing Through Hole Gull-wing Gull-wing
Dig August EEWORLD will have a special feature for you!
2010 is destined to be an extraordinary year. In this year, NXP fully sponsored the EEWORLD 2010 Passionate Innovation Tour. "The chirping of cicadas in the forest makes it even quieter, and the singi...
EEWORLD社区 Suggestions & Announcements
Xilinx FPGA download line schematic
Please help me look at this picture. There are a few things in it that I don't quite understand.Are the diodes D1 and D2 just for protection? I measured the voltage at the VCC sense end and it was abo...
hpfei77 FPGA/CPLD
Low-key earning points
...
fyj012 Embedded System
How to arrange coupling capacitors? See here
How to arrange coupling capacitors? What are the principles? Should a 0.1uf capacitor be placed on each power pin? Sometimes I see 0.1uf and 10uf used together. Why? Answer: The capacitor is close to ...
pan潘 PCB Design
04 Provincial Competition Electrical Design Topic Elevator MCU Program
[i=s] This post was last edited by paulhyde on 2014-9-15 04:04 [/i] This was made using the board issued by NEC (now Renesas) in the national competition. I didn't pay special attention to the pin fun...
shaxiaoziningyi Electronics Design Contest
LED packaging quality control
[size=10.5pt][font=宋体][size=5]The problems that may occur in the LED packaging process are pointed out one by one, and solutions are proposed, focusing on the impact of the packaging position on the L...
songbo PCB Design

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 40  1896  1538  128  1123  1  39  31  3  23 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号