Changes to Ordering Guide .......................................................... 16
9/04—Initial Version: Revision 0
Rev. B | Page 2 of 16
Data Sheet
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; V
REF
= VDD; T
A
= –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Analog Input CMRR
Leakage Current at 25°C
Input Impedance
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
DCLOCK Frequency
REFERENCE
Voltage Range
Load Current
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
Input Capacitance
DIGITAL OUTPUTS
Data Format
V
OH
V
OL
POWER SUPPLIES
VDD
VDD Range
1
Operating Current
VDD
Standby Current
2, 3
Power Dissipation
Conditions
Min
16
0
−0.1
−0.1
AD7683
All Grades
Typ
Max
AD7683
Unit
Bits
V
V
V
dB
nA
+IN − (–IN)
+IN
−IN
f
IN
= 100 kHz
Acquisition phase
V
REF
VDD + 0.1
0.1
65
1
See the Analog Input section
10
100
2.9
VDD + 0.3
50
0
0
0.5
100 kSPS, V
+IN
− V
−IN
= V
REF
/2 = 2.5 V
µs
kSPS
MHz
V
µA
−0.3
0.7 × VDD
−1
−1
5
0.3 × VDD
VDD + 0.3
+1
+1
V
V
µA
µA
pF
I
SOURCE
= −500 µA
I
SINK
= +500 µA
Specified performance
100 kSPS throughput
VDD = 5 V
VDD = 2.7 V
VDD = 5 V, 25°C
VDD = 5 V
VDD = 2.7 V
VDD = 2.7 V, 10 kSPS throughput
2
T
MIN
to T
MAX
Serial, 16 bits straight binary
VDD − 0.3
0.4
2.7
2.0
800
560
1
4
1.5
150
−40
5.5
5.5
V
V
V
V
µA
µA
nA
mW
mW
µW
°C
50
6
TEMPERATURE RANGE
Specified Performance
1
2
+85
See the Typical Performance Characteristics section for more information.
With all digital inputs forced to VDD or GND, as required.
3
During acquisition phase.
Rev. B | Page 3 of 16
AD7683
VDD = 5 V; V
REF
= VDD; T
A
= –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
ACCURACY
No Missing Codes
Integral Linearity Error
Transition Noise
Gain Error
1
, T
MIN
to T
MAX
Gain Error Temperature Drift
Offset Error
1
, T
MIN
to T
MAX
Offset Temperature Drift
Power Supply Sensitivity
AC ACCURACY
Signal-to-Noise
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Effective Number of Bits
1
2
Data Sheet
Conditions
Min
15
−6
A Grade
Typ
Max
Min
16
−3
B Grade
Typ
Max
Unit
Bits
LSB
LSB
LSB
ppm/°C
mV
ppm/°C
LSB
dB
2
dB
dB
dB
Bits
VDD = 5 V
±
5%
f
IN
= 1 kHz
f
IN
= 1 kHz
f
IN
= 1 kHz
f
IN
= 1 kHz
f
IN
= 1 kHz
±3
0.5
±2
±0.3
±0.7
±0.3
±0.05
90
−100
−100
90
14.7
+6
±24
±1.6
±1
0.5
±2
±0.3
±0.4
±0.3
±0.05
91
−108
−106
91
14.8
+3
±15
±1.6
88
88
See the Terminology section. These specifications include full temperature range variation but do not include the error contribution from the external reference.
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
VDD = 2.7 V; V
REF
= 2.5V; T
A
= –40°C to +85°C, unless otherwise noted.
Table 4.
Parameter
ACCURACY
No Missing Codes
Integral Linearity Error
Transition Noise
Gain Error
1
, T
MIN
to T
MAX
Gain Error Temperature Drift
Offset Error
1
, T
MIN
to T
MAX
Offset Temperature Drift
Power Supply Sensitivity
AC ACCURACY
Signal-to-Noise
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Effective Number of Bits
1
2
Conditions
Min
15
−6
A Grade
Typ
Max
Min
16
−3
B Grade
Typ
Max
Unit
Bits
LSB
LSB
LSB
ppm/°C
mV
ppm/°C
LSB
dB
2
dB
dB
dB
Bits
VDD = 2.7 V
±5%
f
IN
= 1 kHz
f
IN
= 1 kHz
f
IN
= 1 kHz
f
IN
= 1 kHz
f
IN
= 1 kHz
±3
0.85
±2
±0.3
±0.7
±0.3
±0.05
85
−96
−94
85
13.8
+6
±30
±3.5
±1
0.85
±2
±0.3
±0.7
±0.3
±0.05
86
−100
−98
86
14
+3
±15
±3.5
See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Rev. B | Page 4 of 16
Data Sheet
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; T
A
= −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter
Throughput Rate
CS Falling to DCLOCK Low
CS Falling to DCLOCK Rising
DCLOCK Falling to Data Remains Valid
CS Rising Edge to D
OUT
High Impedance
DCLOCK Falling to Data Valid
Acquisition Time
D
OUT
Fall Time
D
OUT
Rise Time
Symbol
t
CYC
t
CSD
t
SUCS
t
HDO
t
DIS
t
EN
t
ACQ
t
F
t
R
Min
Typ
Max
100
0
AD7683
20
5
16
14
16
11
11
100
50
25
25
400
Unit
kHz
μs
ns
ns
ns
ns
ns
ns
ns
Timing and Circuit Diagrams
t
CYC
CS
COMPLETE CYCLE
t
SUCS
POWER DOWN
DCLOCK
1
4
5
t
ACQ
t
CSD
D
OUT
HIGH-Z
0
t
EN
t
HDO
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
t
DIS
HIGH-Z
D15 D14 D13 D12 D11 D10 D9
Figure 2. Serial Interface Timing
500µA
I
OL
TO D
OUT
1.4V
C
L
100pF
500µA
I
OH
04301-003
Figure 3. Load Circuit for Digital Interface Timing
2V
0.8V
t
EN
2V
0.8V
t
EN
2V
0.8V
04301-004
Figure 4. Voltage Reference Levels for Timing
D
OUT
90%
04301-006
10%
t
R
t
F
Figure 5. D
OUT
Rise and Fall Timing
Rev. B | Page 5 of 16
04301-002
(MSB)
(LSB)
NOTES
1. A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
D
OUT
GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
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