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EPM570F256C5N

Description
Number of macro cells: 440 Programmable type: In-system programmable I/O number: 160 Number of logic elements/blocks: 570 Operating temperature: 0℃ ~ 85℃ (TJ)
CategoryThe embedded processor and controller    CPLD/FPGA   
File Size737KB,86 Pages
ManufacturerALTERA
Websitehttp://www.altera.com/
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EPM570F256C5N Overview

Number of macro cells: 440 Programmable type: In-system programmable I/O number: 160 Number of logic elements/blocks: 570 Operating temperature: 0℃ ~ 85℃ (TJ)

EPM570F256C5N Parametric

Parameter NameAttribute value
Number of macro cells440
Programmable typeIn-system programmable
Number of I/Os160
Number of logic elements/blocks570
Operating temperature0℃ ~ 85℃ (TJ)
Section I. MAX II Device Family Data
Sheet
This section provides designers with the data sheet specifications for MAX
®
II devices.
The chapters contain feature definitions of the internal architecture, Joint Test Action
Group (JTAG) and in-system programmability (ISP) information, DC operating
conditions, AC timing parameters, and ordering information for MAX II devices.
This section includes the following chapters:
Chapter 1, Introduction
Chapter 2, MAX II Architecture
Chapter 3, JTAG and In-System Programmability
Chapter 4, Hot Socketing and Power-On Reset in MAX II Devices
Chapter 5, DC and Switching Characteristics
Chapter 6, Reference and Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information about when
each chapter was updated, refer to the Chapter Revision Dates section, which appears
in the complete handbook.
© October 2008
Altera Corporation
MAX II Device Handbook
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