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S29GL128P90TFIR20

Categorystorage    The FLASH memory   
File Size904KB,82 Pages
ManufacturerCypress Semiconductor
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S29GL01GP
S29GL512P
S29GL256P
S29GL128P
1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash
with 90 nm MirrorBit Process Technology
General Description
The Cypress S29GL01G/512/256/128P are Mirrorbit
®
Flash products fabricated on 90 nm process technology. These devices
offer a fast page access time of 25 ns with a corresponding random access time as fast as 90 ns. They feature a Write Buffer that
allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than
standard programming algorithms. This makes these devices ideal for today’s embedded applications that require higher density,
better performance and lower power consumption.
Distinctive Characteristics
Single 3V read/program/erase (2.7-3.6 V)
Enhanced VersatileI/O™ control
– All input levels (address, control, and DQ input levels) and
outputs are determined by voltage on V
IO
input. V
IO
range is 1.65
to V
CC
90 nm MirrorBit process technology
8-word/16-byte page read buffer
32-word/64-byte write buffer reduces overall programming time for
multiple-word updates
Secured Silicon Sector region
– 128-word/256-byte sector for permanent, secure identification
through an 8-word/16-byte random Electronic Serial Number
– Can be programmed and locked at the factory or by the
customer
Uniform 64 Kword/128 Kbyte Sector Architecture
– S29GL01GP: One thousand twenty-four sectors
– S29GL512P: Five hundred twelve sectors
– S29GL256P: Two hundred fifty-six sectors
– S29GL128P: One hundred twenty-eight sectors
100,000 erase cycles per sector typical
20-year data retention typical
Offered Packages
– 56-pin TSOP
– 64-ball Fortified BGA
Suspend and Resume commands for Program and Erase
operations
Write operation status bits indicate program and erase operation
completion
Unlock Bypass Program command to reduce programming time
Support for CFI (Common Flash Interface)
Persistent and Password methods of Advanced Sector Protection
WP#/ACC input
– Accelerates programming time (when V
HH
is applied) for greater
throughput during system production
– Protects first or last sector regardless of sector protection
settings
Hardware reset input (RESET#) resets device
Ready/Busy# output (RY/BY#) detects program or erase cycle
completion
Performance Characteristics
Maximum Read Access Times (ns)
Density
Voltage Range
(1)
Regulated V
CC
128 & 256 Mb
Full V
CC
VersatileIO V
IO
Regulated V
CC
512 Mb
Full V
CC
VersatileIO V
IO
Regulated V
CC
1 Gb
Full V
CC
VersatileIO V
IO
Random Access
Time (t
ACC
)
90
100/110
110
100
110
120
110
120
130
Page Access Time
(t
PACC
)
25
CE# Access Time OE# Access Time
(t
CE
)
(t
OE
)
90
100/110
110
100
25
25
110
120
110
25
25
120
130
25
Notes
1.
Access times are dependent on V
CC
and V
IO
operating ranges.
See
Ordering Information
page for further details.
Regulated V
CC
: V
CC
= 3.0–3.6 V.
Full V
CC
: V
CC
= V
IO
= 2.7–3.6 V.
VersatileIO V
IO
: V
IO
= 1.65–V
CC
, V
CC
= 2.7–3.6 V.
2. Contact a sales representative for availability.
Cypress Semiconductor Corporation
Document Number: 002-00886 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 22, 2017
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