FM18W08
256-Kbit (32 K × 8) Wide Voltage Bytewide
F-RAM Memory
2-Mbit (128 K × 16) F-RAM Memory
Features
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Industrial temperature: –40
C
to +85
C
28-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
256-Kbit ferroelectric random access memory (F-RAM)
logically organized as 32 K × 8
14
❐
High-endurance 100 trillion (10 ) read/writes
❐
151-year data retention (see the
Data Retention and
Endurance
table)
❐
NoDelay™ writes
❐
Advanced high-reliability ferroelectric process
SRAM and EEPROM compatible
❐
Industry-standard 32 K × 8 SRAM and EEPROM pinout
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70-ns access time, 130-ns cycle time
Superior to battery-backed SRAM modules
❐
No battery concerns
❐
Monolithic reliability
❐
True surface mount solution, no rework steps
❐
Superior for moisture, shock, and vibration
❐
Resistant to negative voltage undershoots
Low power consumption
❐
Active current 12 mA (max)
❐
Standby current 20
A
(typ)
Wide voltage operation: V
DD
= 2.7 V to 5.5 V
Functional Overview
The FM18W08 is a 32 K × 8 nonvolatile memory that reads and
writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM18W08 operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Minimum read and write cycle times
are equal. The F-RAM memory is nonvolatile due to its unique
ferroelectric memory process. These features make the
FM18W08 ideal for nonvolatile memory applications requiring
frequent or rapid writes.
The device is available in a 28-pin SOIC surface mount package.
Device specifications are guaranteed over the industrial
temperature range –40 °C to +85 °C.
For a complete list of related documentation, click
here.
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Logic Block Diagram
A14-0
Address Latch and Decoder
A 14-0
32 K x 8
F-RAM Array
CE
WE
OE
Control
Logic
I/O Latch & Bus Driver
DQ 7-0
Cypress Semiconductor Corporation
Document Number: 001-86207 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 13, 2014
FM18W08
Contents
Pinout ................................................................................
Pin Definitions ..................................................................
Device Operation ..............................................................
Memory Architecture ...................................................
Memory Operation.......................................................
Read Operation ...........................................................
Write Operation ...........................................................
Pre-charge Operation..................................................
Endurance .........................................................................
F-RAM Design Considerations........................................
Maximum Ratings.............................................................
Operating Range...............................................................
DC Electrical Characteristics ..........................................
Data Retention and Endurance .......................................
Capacitance ......................................................................
Thermal Resistance..........................................................
AC Test Conditions ..........................................................
3
3
4
4
4
4
4
4
4
5
7
7
7
7
8
8
8
AC Switching Characteristics ......................................... 9
SRAM Read Cycle ...................................................... 9
SRAM Write Cycle..................................................... 10
Power Cycle Timing ....................................................... 12
Functional Truth Table................................................... 13
Ordering Information...................................................... 14
Ordering Code Definitions ......................................... 14
Package Diagram............................................................ 15
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community................................. 18
Technical Support ..................................................... 18
Document Number: 001-86207 Rev. *D
Page 2 of 18
FM18W08
Pinout
Figure 1. 28-pin SOIC pinout
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-pin SOIC
(x 8)
Top view
(not to scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
Pin Definitions
Pin Name
A
14
–A
0
DQ
7
–DQ
0
WE
CE
I/O Type
Input
Input
Input
Description
Address inputs:
The 15 address lines select one of 32,768 bytes in the F-RAM array.
Write Enable:
A write cycle begins when WE is asserted. Asserting WE LOW causes the FM18W08 to
write the contents of the data bus to the address location latched by the falling edge of CE.
Chip Enable:
The device is selected when CE is LOW. Asserting CE LOW causes the address to be
latched internally. Address changes that occur after CE goes LOW will be ignored until the next falling
edge occurs.
Output Enable:
When OE is LOW, the FM18W08 drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
Ground for the device. Must be connected to the ground of the system.
No connect. This pin is not connected to the die.
Input/Output
Data I/O Lines:
8-bit bidirectional data bus for accessing the F-RAM array.
OE
V
SS
V
DD
NC
Input
Ground
No connect
Power supply Power supply input to the device.
Document Number: 001-86207 Rev. *D
Page 3 of 18
FM18W08
data. If OE is asserted before completing the memory access,
the data bus will not be driven until valid data is available. This
feature minimizes supply current in the system by eliminating
transients caused by invalid data being driven to the bus. When
OE is deasserted HIGH, the data bus will remain in a HI-Z state.
Device Operation
The FM18W08 is a bytewide F-RAM memory logically organized
as 32,768 × 8 and accessed using an industry-standard parallel
interface. All data written to the part is immediately nonvolatile
with no delay. Functional operation of the F-RAM memory is the
same as SRAM type devices, except the FM18W08 requires a
falling edge of CE to start each memory cycle. See the
Functional Truth Table on page 13
for a complete description of
read and write modes.
Write Operation
In the FM18W08, writes occur in the same interval as reads. The
FM18W08 supports both CE and WE controlled write cycles. In
both cases, the address is latched on the falling edge of CE.
In a CE-controlled write, the WE signal is asserted before
beginning the memory cycle. That is, WE is LOW when the
device is activated with the chip enable. In this case, the device
begins the memory cycle as a write. The FM18W08 will not drive
the data bus regardless of the state of OE.
In a WE-controlled write, the memory cycle begins on the falling
edge of CE. The WE signal falls after the falling edge of CE.
Therefore, the memory cycle begins as a read. The data bus will
be driven according to the state of OE until WE falls. The CE and
WE controlled write timing cases are shown in the
page 12.
Write access to the array begins asynchronously after the
memory cycle is initiated. The write access terminates on the
rising edge of WE or CE, whichever comes first. A valid write
operation requires the user to meet the access time specification
before deasserting WE or CE. The data setup time indicates the
interval during which data cannot change before the end of the
write access.
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Therefore, any operation including read or write
can occur immediately following a write. Data polling, a
technique used with EEPROMs to determine if a write is
complete, is unnecessary.
Memory Architecture
Users access 32,768 memory locations, each with 8 data bits
through a parallel interface. The complete 15-bit address
specifies each of the 8,192 bytes uniquely. The F-RAM array is
organized as 4092 rows of 8-bytes each. This row segmentation
has no effect on operation, however the user can group data into
blocks by its endurance characteristics as explained in the
Endurance
section.
The cycle time is the same for read and write memory
operations. This simplifies memory controller logic and timing
circuits. Likewise the access time is the same for read and write
memory operations. When CE is deasserted HIGH, a pre-charge
operation begins, and is required of every memory cycle. Thus
unlike SRAM, the access and cycle times are not equal. Writes
occur immediately at the end of the access with no delay. Unlike
an EEPROM, it is not necessary to poll the device for a ready
condition since writes occur at bus speed.
It is the user’s responsibility to ensure that V
DD
remains within
datasheet tolerances to prevent incorrect operation. Also proper
voltage level and timing relationships between V
DD
and CE must
be maintained during power-up and power-down events. See
“Power Cycle Timing”
on page 12.
Memory Operation
The FM18W08 is designed to operate in a manner similar to
other bytewide memory products. For users familiar with
BBSRAM, the performance is comparable but the bytewide
interface operates in a slightly different manner as described
below. For users familiar with EEPROM, the differences result
from the higher write performance of F-RAM technology
including NoDelay writes and much higher write endurance.
Pre-charge Operation
The pre-charge operation is an internal condition in which the
memory state is prepared for a new access. All memory cycles
consist of a memory access and a pre-charge. Pre-charge is
user-initiated by driving the CE signal HIGH. It must remain
HIGH for at least the minimum pre-charge time, t
PC
.
The user determines the beginning of this operation since a
pre-charge will not begin until CE rises. However, the device has
a maximum CE LOW time specification that must be satisfied.
Read Operation
A read operation begins on the falling edge of CE. At this time,
the address bits are latched and a memory cycle is initiated.
Once started, a full memory cycle must be completed internally
even if CE goes inactive. Data becomes available on the bus
after the access time is met.
After the address has been latched, the address value may be
changed upon satisfying the hold time parameter. Unlike an
SRAM, changing address values will have no effect on the
memory operation after the address is latched.
The FM18W08 will drive the data bus when OE is asserted LOW
and the memory access time is met. If OE is asserted after the
memory access time is met, the data bus will be driven with valid
Document Number: 001-86207 Rev. *D
Endurance
Internally, a F-RAM operates with a read and restore
mechanism. Therefore, each read and write cycle involves a
change of state. The memory architecture is based on an array
of rows and columns. Each read or write access causes an
endurance cycle for an entire row. In the FM18W08, a row is 64
bits wide. Every 8-byte boundary marks the beginning of a new
row. Endurance can be optimized by ensuring frequently
accessed data is located in different rows. Regardless, F-RAM
Page 4 of 18
FM18W08
offers substantially higher write endurance than other nonvolatile
memories. The rated endurance limit of 10
14
cycles will allow
150,000 accesses per second to the same row for over 20 years.
Users who are modifying existing designs to use F-RAM should
examine the memory controller for timing compatibility of
address and control pins. Each memory access must be
qualified with a LOW transition of CE. In many cases, this is the
only change required. An example of the signal relationships is
shown in
Figure 2
below. Also shown is a common SRAM signal
relationship that will not work for the FM18W08.
The reason for CE to strobe for each address is twofold: it latches
the new address and creates the necessary pre-charge period
while CE is HIGH.
F-RAM Design Considerations
When designing with F-RAM for the first time, users of SRAM will
recognize a few minor differences. First, bytewide F-RAM
memories latch each address on the falling edge of chip enable.
This allows the address bus to change after starting the memory
access. Since every access latches the memory address on the
falling edge of CE, users cannot ground it as they might with
SRAM.
Figure 2. Chip Enable and Memory Address Relationships
Valid Strobing of CE
CE
F-RAM
Signaling
Address
A1
A2
Data
D1
D2
Invalid Strobing of CE
CE
SRAM
Signaling
Address
A1
A2
Data
D1
D2
A second design consideration relates to the level of V
DD
during
operation. Battery-backed SRAMs are forced to monitor V
DD
in
order to switch to battery backup. They typically block user
access below a certain V
DD
level in order to prevent loading the
battery with current demand from an active SRAM. The user can
be abruptly cut off from access to the nonvolatile memory in a
power down situation with no warning or indication.
F-RAM memories do not need this system overhead. The
memory will not block access at any V
DD
level that complies with
the specified operating range. The user should take measures to
prevent the processor from accessing memory when V
DD
is
out-of-tolerance. The common design practice of holding a
processor in reset during power-down may be sufficient. It is
recommended that chip enable is pulled HIGH and allowed to
track V
DD
during power-up and power-down cycles. It is the
user’s responsibility to ensure that chip enable is HIGH to
prevent accesses below V
DD
min. (2.7 V).
Figure 3
shows a pull-up resistor on CE, which will keep the pin
HIGH during power cycles, assuming the MCU / MPU pin
Document Number: 001-86207 Rev. *D
tristates during the reset condition. The pull-up resistor value
should be chosen to ensure the CE pin tracks V
DD
to a high
enough value, so that the current drawn when CE is LOW is not
an issue.
Figure 3. Use of Pull-up Resistor on CE
VDD
FM18W08
CE
WE
MCU / MPU
OE
A 14-0
DQ 7-0
Page 5 of 18
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