FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00043-2v0-E
Memory FRAM
4 M (512 K
×
8) Bit Quad SPI
MB85RQ4ML
■
DESCRIPTION
MB85RQ4ML is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 524,288
words
×
8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the
nonvolatile memory cells.
MB85RQ4ML adopts the Quad Serial Peripheral Interface (QSPI) which can realize a high bandwidth such
as Read and Write at 54 MB/s using four bi-directional pins (Quad I/O).
The MB85RQ4ML is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85RQ4ML can be used for 10
13
read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E
2
PROM.
MB85RQ4ML does not take long time to write data like Flash memories or E
2
PROM.
MB85RQ4ML is able to write data at a high bandwidth without any waiting time and fits perfectly into
Networking, Gaming, Industrial computing, Camera, RAID controllers, etc.
■
FEATURES
• Bit configuration
• Serial Peripheral Interface
•
•
•
•
•
•
•
•
•
: 524,288 words
×
8 bits
: SPI (Serial Peripheral Interface) / Quad SPI
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
Write supports
: Single data input / Quad data input / Quad address and data input /
QPI mode
Read supports
: Single data output / Fast single data output / Fast quad data output /
Fast quad address input and data output / QPI mode / XIP mode
Operating frequency
: 108 MHz (Except normal READ command)
High endurance
: 10
13
Read/Write per byte
Data retention
: 10 years (+85
°C),
95 years (
+
55
°C),
over 200 years (
+
35
°C)
Operating power supply voltage : 1.7 V to 1.95 V (Single power supply)
Power consumption
: Operating power supply current 20.0 mA (Typ@Quad I/O 108 MHz)
Standby current 70
μA
(Typ), 400
μA
(Max)
Operation ambient temperature range : -40
°C
to +85
°C
Package
: 16-pin plastic SOP (FPT-16P-M24)
RoHS compliant
Copyright 2016 FUJITSU SEMICONDUCTOR LIMITED
2016.10
MB85RQ4ML
■
PIN ASSIGNMENT
(TOP VIEW)
HOLD (IO3)
VDD
NC
NC
NC
NC
CS
SO (IO1)
SCK
SI (IO0)
NC
NC
NC
NC
VSS
WP (IO2)
(FPT-16P-M24)
NC: Non connect pin
■
PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name
Functional description
Chip Select pin
This is an input pin to make chips select. When CS is “H” level, device is in deselect
(standby) status and SO becomes High-Z. Inputs from other pins are ignored for this
time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before
inputting op-code. The Chip Select pin is pulled up internally to the VDD pin via a resistor.
Write Protect pin except in Quad SPI mode
This is a pin to control writing to a status register. The writing of status register (see “■
STATUS REGISTER”) is protected in related with WP and WPEN bit of the status
register. See “■ WRITING PROTECT” for detail.
(Serial Data Input Output 2 in Quad SPI mode)
Hold pin except in Quad SPI mode
This pin is used to interrupt serial input/output without making chips deselect. When
HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become
“don’t care”. While the hold operation, CS has to be retained “L” level.
(Serial Data Input Output 3 in Quad SPI mode)
Serial Clock pin
This is a clock input pin to input/output serial data. Inputs data are latched synchronously
to a rising edge, Outputs data occur synchronously to a falling edge.
Serial Data Input pin except in Quad SPI mode
This is an input pin of serial data. This inputs op-code, addresses and writing data.
(Serial Data Input Output 0 in Quad SPI mode)
Serial Data Output pin except in Quad SPI mode
This is an output pin of serial data. Reading data of FRAM memory cell array and status
register data are output. This is High-Z during standby.
(Serial Data Input Output 1 in Quad SPI mode)
Supply Voltage pin
Ground pin
7
CS
9
WP
(IO2)
1
HOLD
(IO3)
16
SCK
15
SI
(IO0)
8
SO
(IO1)
VDD
VSS
2
10
* When using Quad SPI mode instructions, the SI, SO, WP and HOLD pins become bidirectional IO0, IO1, IO2
and IO3 pins.
2
DS501-00043-2v0-E
MB85RQ4ML
■
BLOCK DIAGRAM
SCK
Address Counter
Control Circuit
CS
Decoder
FRAM Cell Array
524,288
✕
8
SI (IO0)
SO (IO1)
HOLD (IO3)
Serial I/O Interface
Sense Amp/Write Amp
Data Register
FRAM
Status Register
WP (IO2)
■
SPI MODE
MB85RQ4ML corresponds to the SPI mode 0 (CPOL
=
0, CPHA
=
0) , and SPI mode 3 (CPOL
=
1, CPHA
=
1) .
CS
SCK
SI
7
MSB
6
5
4
3
2
1
0
LSB
SPI Mode 0
CS
SCK
SI
7
MSB
6
5
4
3
2
1
0
LSB
SPI Mode 3
DS501-00043-2v0-E
3
MB85RQ4ML
■
SERIAL PERIPHERAL INTERFACE (SPI)
•
SPI
MB85RQ4ML works as a slave of SPI. SPI uses the SI serial input pin to write op-code, addresses or data
to the device on the rising edge of SCK. The SO serial output pin is used to read data or status register
from the device on the falling edge of SCK.
•
Quad SPI
MB85RQ4ML works as a slave of Quad SPI. MB85RQ4ML supports Quad SPI mode using the “FRQO”,
“FRQAD”, “WQD” and “WQAD” commands, QPI mode using the “EQPI” and “DQPI” commands and XIP
mode. When using Quad SPI mode instructions, the SI, SO, WP and HOLD pins become bidirectional IO0,
IO1, IO2 and IO3 pins.
■
STATUS REGISTER
Bit No.
Bit Name
Function
Status Register Write Protect
This is a bit composed of nonvolatile memory (FRAM). WPEN protects
writing to a status register (refer to “■ WRITING PROTECT”) relating with
WP input. Writing with the WRSR command and reading with the RDSR
command are possible.
QPI mode bit
This is a volatile bit and “0” after power-on and defines QPI mode
enabled/disabled.
1 = QPI mode enabled, set by the EQPI command
0 = QPI mode disabled, reset by the DQPI command
The QPI bit cannot be changed with the WRSR command. Reading with
the RDSR command is possible.
LC (Latency Control) mode bit
These are bits composed of nonvolatile memories.
These define number of dummy cycles for the FRQO and FRQAD com-
mands (refer to “■ LC Mode”).
Writing with the WRSR command and reading with the RDSR
command are possible.
Block Protect
These are bits composed of nonvolatile memories. These define size of
write protect block for the WRITE, WQD and WQAD commands (refer to
“■ BLOCK PROTECT”). Writing with the WRSR command and reading
with the RDSR command are possible.
Write Enable Latch
This is a volatile bit and “0” after power-on and indicates FRAM Array and
status register are writable.
1 =
writable, set by the WREN command
0 =
unwritable, reset by the WRDI command
With the RDSR command, reading is possible but writing is impossible
with the WRSR command.
WEL is reset after the following operations.
After power-on.
After the WRDI command recognition.
At the rising edge of CS after WRSR command recognition.
At the rising edge of CS after WRITE command recognition.
At the rising edge of CS after WQD command recognition.
At the rising edge of CS after WQAD command recognition.
This is a bit fixed to “0”.
7
WPEN
6
QPI
5
LC1
4
LC0
3
2
BP1
BP0
1
WEL
0
0
4
DS501-00043-2v0-E
MB85RQ4ML
■
OP-CODE
MB85RQ4ML accepts 8 kinds of SPI Mode command, 4 kinds of Quad SPI Mode command and 2 kinds
of QPI Mode command specified in op-code. Op-code is a code composed of 8 bits shown in the table
below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code, the command
are not performed.
Mode Name
Description
Op-code
Max Freq. (MHz)
QPI
XIP
WREN
WRDI
RDSR
SPI
WRSR
READ
RDID
FRQO
Quad
SPI
WQD
EQPI
DQPI
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read
Read Device ID
Fast Read Quad Output
Write Quad Data
Enable QPI mode
Disable QPI mode
0000 0110
B
0000 0100
B
0000 0101
B
0000 0001
B
0000 0011
B
0000 0010
B
1001 1111
B
0000 1011
B
0110 1011
B
1110 1011
B
0011 0010
B
0001 0010
B
0011 1000
B
1111 1111
B
108
108
108
108
40
108
108
108
108*
108*
108
108
108
108
Yes
Yes
Yes
No
No
No
No
No
No
Yes
No
Yes
No
Yes
No
No
No
No
No
No
No
Yes
Yes
Yes
No
No
No
No
WRITE Write
FSTRD Fast Read Memory Code
FRQAD Fast Read Quad Address and Data
WQAD Write Quad Address and Data
QPI
*: The frequency when the number of dummy cycles is default value of 6 (see “■ LC MODE”).
Notes
1. “Yes”: Commands are supported in this mode, “No”: Commands are not supported.
2. FRQAD command cannot be issued as 1
st
command after power-on. Any other command shall be issued
at least once before FRQAD command.
3-1. Single Input Address (3bytes)
SI= X, X, X, X, X, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0
(Upper 5bit = any)
3-2. Quad Input Address (3bytes)
IO0=X, A16, A12, A8, A4, A0
IO1=X, A17, A13, A9, A5, A1
IO2=X, A18, A14, A10, A6, A2
IO3=X, X, A15, A11, A7, A3
(Upper 5bit = any)
4-1. Single I/O Data
SI (or SO)=D7, D6, D5, D4, D3, D2, D1, D0
4-2. Quad I/O Data
IO0=D4, D0
IO1=D5, D1
IO2=D6, D2
IO3=D7, D3
DS501-00043-2v0-E
5
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