FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20894-1E
FLASH MEMORY
CMOS
32 M (4 M
×
8/2 M
×
16) BIT
MBM29LV320TE
80/90/10
MBM29LV320BE
80
/
90
/
10
s
DESCRIPTION
The MBM29LV320TE/BE is 32 M-bit, 3.0 V-only Flash memory organized as 4 M bytes of 8 bits each or 2 M words
of 16 bits each. The device is offered in a 48-pin TSOP (I) and 63-ball FBGA packages. This device is designed
to be programmed in-system with the standard system 3.0 V V
CC
supply. 12.0 V V
PP
and 5.0 V V
CC
are not required
for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.
The standard device offers access times 80 ns, 90 ns and 100 ns, allowing operation of high-speed microproces-
sors without wait state. To eliminate bus contention the device has separate chip enable(CE), write enable(WE)
and output enable (OE) controls.
(Continued)
s
PRODUCT LINE UP
Part No.
Power Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
80
80
30
MBM29LV320TE/BE
80
V
CC
=
3.3 V
+0.3
V
−0.3
V
90
90
35
90
100
V
CC
=
3.0 V
+0.6
V
−0.3
V
100
100
35
s
PACKAGES
48-pin plastic TSOP (I)
Marking Side
48-pin plastic TSOP (I)
63-ball plastic FBGA
(FPT-48P-M19)
Marking Side
(FPT-48P-M20)
(BGA-63P-M01)
MBM29LV320TE/BE
80/90/10
(Continued)
The device is pin and command set compatible with JEDEC standard E
2
PROMs. Commands are written to the
command register using standard microprocessor write timings. Register contents serve as input to an internal
state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase operations. Reading data out of the device is similar to reading
from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This will invoke the Embedded
Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is
accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which
is an internal algorithm that automatically preprograms the array if it is not already programmed before executing
the erase operation. During erase, the device automatically time the erase pulse widths and verify proper cell
margin.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the device internally resets to the read mode.
The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program
Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read
mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the
Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode
and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up
firmware from the Flash memory.
Fujitsu’s Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The device memory electrically erase the entire chip or all bits within
a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a
time using the EPROM programming mechanism of hot electron injection.
2
MBM29LV320TE/BE
80/90/10
s
FEATURES
•
0.23
µ
m Process Technology
•
Single 3.0 V read, program, and erase
Minimized system level power requirements
•
Compatible with JEDEC-standard commands
Use the same software commands as E
2
PROMs
•
Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (I) (Package suffix : TN
−
Normal Bend Type, TR
−
Reversed Bend Type)
63-ball FBGA (Package suffix : PBT)
•
Minimum 100,000 program/erase cycles
•
High performance
80 ns maximum access time
•
Sector erase architecture
Eight 4 K word and sixty-three 32 K word sectors in word mode
Eight 8 K byte and sixty-three 64 K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
•
Boot Code Sector Architecture
T
=
Top sector
B
=
Bottom sector
•
Hidden ROM (Hi-ROM) region
256 byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
•
WP/ACC input pin
At V
IL
, allows protection of boot sectors, regardless of sector protection/unprotection status
At V
IH
, allows removal of boot sector protection
At V
ACC
, increases program performance
•
Embedded Erase
TM
* Algorithms
Automatically pre-programs and erases the chip or any sector
•
Embedded Program
TM
* Algorithms
Automatically writes and verifies data at specified address
•
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
•
Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
•
Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
•
Low V
CC
write inhibit
≤
2.5 V
•
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
•
Sector group protection
Hardware method disables any combination of sector groups from program or erase operations
•
Sector Group Protection Set function by Extended sector group protection command
•
Fast Programming Function by Extended Command
•
Temporary sector group unprotection
Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)
*
: Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices
,
Inc.
3
MBM29LV320TE/BE
80/90/10
s
PIN ASSIGNMENTS
TSOP (I)
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
19
A
20
WE
RESET
N.C.
WP/ACC
RY/BY
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Marking Side)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A
16
BYTE
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE
V
SS
CE
A
0
MBM29LV320TE/BE
Normal Bend
(FPT-48P-M19)
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
17
A
18
RY/BY
WP/ACC
N.C.
RESET
WE
A
20
A
19
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
MBM29LV320TE/BE
Reverse Bend
A
0
CE
V
SS
OE
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
V
CC
DQ
4
DQ
12
DQ
5
DQ
13
DQ
6
DQ
14
DQ
7
DQ
15
/A
-1
V
SS
BYTE
A
16
(FPT-48P-M20)
(Continued)
4
MBM29LV320TE/BE
80/90/10
(Continued)
FBGA
(TOP VIEW)
Marking Side
A8
N.C.
A7
N.C.
B8
N.C.
B7
N.C.
C7
A
13
C6
A
9
C5
D7
A
12
D6
A
8
D5
E7
A
14
E6
A
10
E5
F7
A
15
F6
A
11
F5
A
19
F4
A
20
F3
A
5
F2
A
1
G7
A
16
G6
H7
J7
K7
L8
N.C.
L7
N.C.
M8
N.C.
M7
N.C.
BYTE DQ
15
/ V
SS
A
-1
H6
J6
K6
DQ
7
DQ
14
DQ
13
DQ
6
G5
H5
J5
V
CC
J4
K5
DQ
4
K4
WE RESET N.C.
C4
D4
E4
A
18
E3
A
6
E2
A
2
DQ
5
DQ
12
G4
H4
RY/BY WP/
ACC
C3
A
7
A2
N.C.
A1
N.C.
B1
N.C.
C2
A
3
D3
A
17
D2
A
4
DQ
2
DQ
10
DQ
11
DQ
3
G3
DQ
0
G2
A
0
H3
DQ
8
H2
CE
J3
DQ
9
J2
OE
K3
DQ
1
K2
V
SS
L2
N.C.
L1
N.C.
M2
N.C.
M1
N.C.
(BGA-63P-M01)
5
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