82P33731ABAG datasheet, PDF - EEWORLD Datasheet

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82P33731ABAG: CategoryAnalog mixed-signal IC The clock/timer - special; File Size835KB，65 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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Synchronous Equipment Timing Source

for 10G/40G/100G Synchronous Ethernet

HIGHLIGHTS

•

82P33731

Datasheet

Synchronous Equipment Timing Source (SETS) for Synchronous

Ethernet (SyncE) per ITU-T G.8264

DPLL1 generates ITU-T G.8262 compliant SyncE clocks, Telcordia

GR-1244-CORE/GR-253-CORE, and ITU-T G.813 compliant SONET/

SDH clocks

DPLL2 performs rate conversions for synchronization interfaces or for

other general purpose timing applications

APLL3 is Voltage Controlled Crystal Oscillator (VCXO) based and

generates clocks with jitter <0.3 ps RMS (10 kHz to 20 MHz) for:

10GBASE-R, 10GBASE-W, 40GBASE-R and 100GBASE-R

APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to

20 MHz) for: 1000BASE-T and 1000BASE-X

Fractional-N input dividers support a wide range of reference frequen-

cies

Locks to 1 Pulse Per Second (PPS) references

DPLLs, APLL1 and APLL2 can be configured from an external

EEPROM after reset

•

FEATURES

•

Composite clock inputs (IN1 and IN2) accept 64 kHz synchronization

interface signals per ITU-T G.703

Differential reference inputs (IN3 to IN8) accept clock frequencies

between 1 PPS and 650 MHz

Single ended inputs (IN9 to IN14) accept reference clock frequencies

between 1 PPS and 162.5 MHz

Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any

clock reference input

Reference monitors qualify/disqualify references depending on activ-

ity, frequency and LOS pins

Automatic reference selection state machines select the active refer-

ence for each DPLL based on the reference monitors, priority tables,

revertive and non-revertive settings and other programmable settings

Fractional-N input dividers enable the DPLLs to lock to a wide range

of reference clock frequencies including: 10/100/1000 Ethernet, 10G/

40G/100G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI,

and GNSS frequencies

Any reference inputs (IN3 to IN14) can be designated as external sync

pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a select-

able reference clock input

FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses

that are aligned with the selected external input sync pulse input and

frequency locked to the associated reference clock input

DPLL1 can be configured with bandwidths between 0.09 mHz and

567 Hz

DPLL1 locks to input references with frequencies between 1 PPS and

650 MHz

DPLL2 locks to input references with frequencies between 8 kHz and

650 MHz

DPLL1 complies with ITU-T G.8262 for Synchronous Ethernet Equip-

ment Clock (EEC), and G.813 for Synchronous Equipment Clock

(SEC); and Telcordia GR-253-CORE/ GR-1244-CORE for Stratum 3

and SONET Minimum Clock (SMC)

DPLL1 generates clocks with PDH, TDM, GSM, CPRI/OBSAI, 10/100/

1000 Ethernet and GNSS frequencies; these clocks are directly avail-

able on OUT1

DPLL2 generates N x 8 kHz clocks up to 100 MHz that are output on

OUT9 and OUT10

APLL1, APLL2 and APLL3 are connected to DPLL1

APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or

SONET/SDH frequencies

APLL3 generates 10G/40G/100G Ethernet, WAN-PHY, and LAN-PHY

frequencies

Any of eight common TCXO/OCXO frequencies can be used for the

System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz,

24.576 MHz, 25 MHz, or 30.72 MHz

The I2C slave interface can be used by a host processor to access the

control and status registers

The I2C master interface can automatically load a device configura-

tion from an external EEPROM after reset; APLL3 must be configured

via the I2C slave interface

DPLLs can be connected to an internal composite clock generator that

outputs its 64 kHz synchronization signal on OUT8

Differential outputs OUT3 to OUT6 output clocks with frequencies

between 1 PPS and 650 MHz

Differential outputs OUT11 and OUT12 output clocks with frequencies

up to 650 MHz

Single ended outputs OUT1, OUT2 and OUT7 output clocks with fre-

quencies between 1 PPS and 125 MHz

Single ended outputs OUT9 and OUT10 output clocks N*8 kHz multi-

ples up to 100 MHz

DPLL1 supports independent programmable delays for each of IN3 to

IN14; the delay for each input is programmable in steps of 0.61 ns

with a range of ~±78 ns

The input to output phase delay of DPLL1 is programmable in steps of

0.0745 ps with a total range of ±20

s

The clock phase of each of the output dividers for OUT1 (from APLL1)

to OUT7 is individually programmable in steps of ~200 ps with a total

range of +/-180°

1149.1 JTAG Boundary Scan

144-pin CABGA green package

Access routers, edge routers, core routers

Carrier Ethernet switches

Multi-service access platforms

PON OLT

LTE eNodeB

ITU-T G.8264 Synchronous Equipment Timing Source (SETS)

ITU-T G.8262 Synchronous Ethernet Equipment Clock (EEC)

ITU-T G.813 Synchronous Equipment Clock (SEC)

Telcordia GR-253-CORE/GR1244-CORE Stratum 3 Clock (S3) and

SONET Minimum Clock (SMC)

APPLICATIONS

August 28, 2017

82P33731 Datasheet

DESCRIPTION

The 82P33731 Synchronous Equipment Timing Source (SETS) for 10G Synchronous Ethernet (SyncE) provides tools to manage timing refer-

ences, clock generation and timing paths for SyncE based clocks, per ITU-T G.8264 and ITU-T G.8262. 82P33731 meets the requirements of ITU-T

G.8262 for synchronous Ethernet Equipment Clocks (EECs) and ITU-T G.813 for Synchronous Equipment Clocks (SEC). The device outputs low-jit-

ter clocks that can directly synchronize 100GBASE-R, 40GBASE-R, 10GBASE-R and 10GBASE-W and lower-rate Ethernet interfaces; as well as

CPRI/OBSAI, SONET/SDH and PDH interfaces.

The 82P33731 accepts six differential reference inputs and six single ended reference inputs that can operate at common GNSS, Ethernet,

SONET/SDH and PDH frequencies that range from 1 Pulse Per Second (PPS) to 650 MHz. The device also provides two Alternate Mark Inversion

(AMI) inputs for Composite Clock (CC) signals bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The references are continually moni-

tored for loss of signal and for frequency offset per user programmed thresholds. All of the references are available to both Digital PLLs (DPLLs). The

active reference for each DPLL is determined by forced selection or by automatic selection based on user programmed priorities and locking allow-

ances and based on the reference monitors and LOS inputs.

The 82P33731 can accept a clock reference and an associated phase locked sync signal as a pair. DPLL1 can lock to the clock reference and

align the frame sync and multi-frame sync outputs with the paired sync input. The device allows any of the differential or single ended reference inputs

to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. The input sync signals can

have a frequency of 1 PPS, 2 kHz, 4 kHz or 8 kHz. This feature enables DPLL1 to phase align its frame sync and multi-frame sync outputs with a sync

input without the need use a low bandwidth setting to lock directly to the sync input.

The DPLLs support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode the DPLLs synthesize clocks based on

the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term output fre-

quency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL uses frequency data

acquired while in Locked mode to generate accurate frequencies when input references are not available.

The 82P33731 requires a system clock for its reference monitors and other digital circuitry. The frequency accuracy of the system clock deter-

mines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequency stability of the

DPLLs in Free-Run mode and in Holdover mode; and it affects the wander generation of the DPLLs in Locked mode.

When used with a suitable system clock, DPLL1 meets the frequency accuracy, pull-in, hold-in, pullout, noise generation, noise tolerance, tran-

sient response, and holdover performance requirements of the following applications: ITU-T G.8262/G.813 EEC/SEC options 1 and 2, Telcordia GR-

1244 Stratum 3 (S3), Telcordia GR-253-CORE S3 and SONET Minimum Clock (SMC).

DPLL1 can be configured with a range of selectable filtering bandwidths from 0.09 mHz to 567 Hz. The 17 mHz bandwidth can be used to lock the

DPLL directly to a 1 PPS reference. The 92 mHz bandwidth can be used for G.8262/G.813 Option 2, or Telcordia GR-253-CORE S3, or SMC applica-

tions. The bandwidths in the range 1.1 Hz to 8.9 Hz can be used for G.8262/G.813 Option 1 applications. The bandwidth of 1.1 Hz or 2.2 Hz can be

used for Telcordia GR-1244-CORE S3 applications. Bandwidths above 10 Hz can be used in jitter attenuation and rate conversion applications.

DPLL2 is a wideband (BW > 25Hz) frequency translator that can be used, for example, to convert a recovered line clock to a 1.544 MHz or 2.048

MHz synchronization interface clock.

For SETS applications per ITU-T G.8264, DPLL1 is configured as an EEC/SEC to output clocks for the T0 reference point and DPLL2 is used to

output clocks for the T4 reference point.

Clocks generated by DPLL1 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The output

clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces.

Clocks generated by DPLL1 can be passed through APLL3 which is a voltage controlled crystal oscillator (VCXO) based jitter attenuating APLL.

APLL3 can be provisioned with one or two selectable crystal resonators to support up to two base frequencies. The output clocks generated by

APLL3 are suitable for multi-lane 100GBASE-R, 40GBASE-R and lower rate interfaces.

The device provides an AMI output for a CC signal bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The CC output can be con-

nected to either DPLL1 or DPLL3.

All 82P33731 control and status registers are accessed through an I2C slave microprocessor interface. For configuring the DPLLs, APLL1 and

APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset. APLL3 must be configured via the I2C

slave interface.

August 28, 2017

82P33731 Datasheet

CONTENTS

HIGHLIGHTS ........................................................................................................................................................................... 1

FEATURES .............................................................................................................................................................................. 1

APPLICATIONS ....................................................................................................................................................................... 1

DESCRIPTION......................................................................................................................................................................... 2

FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................... 3

CONTENTS.............................................................................................................................................................................. 3

1 PIN ASSIGNMENT ............................................................................................................................................................. 5

2 PIN DESCRIPTION ............................................................................................................................................................ 6

2.1

2.2

2.3

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS ............................................................................................................. 9

2.1.1 Inputs ................................................................................................................................................................................................. 9

2.1.2 Outputs ............................................................................................................................................................................................... 9

RESET OPERATION ..................................................................................................................................................................................... 10

MS/SL PIN USAGE ........................................................................................................................................................................................ 10

3 FUNCTIONAL DESCRIPTION .......................................................................................................................................... 11

3.1

3.2

SYNCHRONOUS ETHERNET (SYNCE), SONET, AND SDH SYSTEM ARCHITECTURES ...................................................................... 11

HARDWARE FUNCTIONAL DESCRIPTION ................................................................................................................................................ 13

3.2.1 System clock .................................................................................................................................................................................... 13

3.2.2 Modes of operation .......................................................................................................................................................................... 13

3.2.2.1 DPLL1 Operating Mode ................................................................................................................................................... 13

3.2.2.1.1 Free-Run Mode ............................................................................................................................................. 15

3.2.2.1.2 Pre-Locked Mode .......................................................................................................................................... 15

3.2.2.1.3 Locked Mode ................................................................................................................................................. 15

3.2.2.1.4 Pre-Locked2 Mode ........................................................................................................................................ 17

3.2.2.1.5 Lost-Phase Mode .......................................................................................................................................... 17

3.2.2.1.6 DCO Control Modes ...................................................................................................................................... 17

3.2.2.1.7 Holdover Mode .............................................................................................................................................. 18

3.2.2.1.8 Hitless Reference Switching .......................................................................................................................... 18

3.2.2.1.9 Phase Slope Limit .......................................................................................................................................... 19

3.2.2.1.10 Frequency Offset Limit .................................................................................................................................. 19

3.2.2.2 DPLL2 Operating Mode ................................................................................................................................................... 19

3.2.2.2.1 Free-Run Mode ............................................................................................................................................. 19

3.2.2.2.2 Locked Mode ................................................................................................................................................. 19

3.2.2.2.3 Holdover Mode .............................................................................................................................................. 19

3.2.2.2.4 Frequency Offset Limit .................................................................................................................................. 20

3.2.3 Input Clocks and frame sync ............................................................................................................................................................ 20

3.2.3.1 Input Clock Pre-divider ..................................................................................................................................................... 20

3.2.3.2 Input Clock Quality Monitoring ......................................................................................................................................... 22

3.2.3.2.1 Loss of Signal (LOS) Monitoring .................................................................................................................... 22

3.2.3.2.2 Activity Monitoring ......................................................................................................................................... 22

3.2.3.2.3 Frequency Monitoring .................................................................................................................................... 23

3.2.3.3 Input Clock Selection ........................................................................................................................................................ 24

3.2.3.3.1 Forced Selection ............................................................................................................................................ 24

3.2.3.3.2 Automatic Selection ....................................................................................................................................... 24

3.2.3.3.2.1Input Clock Validation ................................................................................................................... 24

3.2.3.3.2.2Revertive and Non-Revertive Switching ....................................................................................... 25

3.2.3.3.3 Selected / Qualified Input Clocks Indication .................................................................................................. 25

3.2.3.3.4 Input Clock Loss of Signal ............................................................................................................................. 25

3.2.4 DPLL Locking Process ..................................................................................................................................................................... 25

3.2.4.1 Fast Loss .......................................................................................................................................................................... 25

3.2.4.2 Fine Phase Loss ............................................................................................................................................................... 25

August 28, 2017

82P33731 Datasheet

3.2.5

3.2.6

3.2.7

3.2.8

3.2.4.3 Hard Limit Exceeding .......................................................................................................................................................

3.2.4.4 Locking Status ..................................................................................................................................................................

3.2.4.5 Phase Lock Alarm ............................................................................................................................................................

APLL1 and APLL2 ............................................................................................................................................................................

APLL3 ..............................................................................................................................................................................................

3.2.6.1 External Crystals ..............................................................................................................................................................

Output Clocks & Frame Sync Signals ..............................................................................................................................................

3.2.7.1 Output Clocks ...................................................................................................................................................................

3.2.7.2 Frame Sync Signals .........................................................................................................................................................

Input and output Phase control ........................................................................................................................................................

3.2.8.1 DPLL1 and DPL2 Phase offset control .............................................................................................................................

3.2.8.2 Input Phase control ..........................................................................................................................................................

3.2.8.3 Output Phase control ........................................................................................................................................................

4 POWER SUPPLY FILTERING TECHNIQUES ................................................................................................................. 32

5 MICROPROCESSOR INTERFACE .................................................................................................................................. 34

5.1

I2C SLAVE MODE ......................................................................................................................................................................................... 34

5.1.1 I2C Device Address ......................................................................................................................................................................... 34

5.1.2 I2C Bus Timing ................................................................................................................................................................................. 34

5.1.3 Supported Transactions ................................................................................................................................................................... 36

I2C MASTER MODE ...................................................................................................................................................................................... 36

5.2.1 I2C Boot-up Initialization Mode ........................................................................................................................................................ 37

5.2.2 EEPROM memory map notes .......................................................................................................................................................... 37

5.2

6 JTAG ................................................................................................................................................................................. 38

7 THERMAL MANAGEMENT .............................................................................................................................................. 39

8 ELECTRICAL SPECIFICATIONS ..................................................................................................................................... 40

8.1

8.2

8.3

ABSOLUTE MAXIMUM RATING ................................................................................................................................................................... 40

RECOMMENDED OPERATION CONDITIONS ............................................................................................................................................ 40

I/O SPECIFICATIONS ................................................................................................................................................................................... 41

8.3.1 AMI Input / Output Port .................................................................................................................................................................... 41

8.3.1.1 Structure ........................................................................................................................................................................... 41

8.3.1.2 I/O Level ........................................................................................................................................................................... 41

8.3.1.3 Over-Voltage Protection ................................................................................................................................................... 42

8.3.2 CMOS Input / Output Port ................................................................................................................................................................ 42

8.3.3 LVPECL / LVDS Input / Output Port ................................................................................................................................................. 43

8.3.3.1 PECL Input Port ............................................................................................................................................................... 43

8.3.3.2

LVPECL Output Port .................................................................................................................................................... 44

8.3.3.2.1 LVPECL Termination for 3.3 V ...................................................................................................................... 44

8.3.3.2.2 LVPECL Termination for 2.5 V ...................................................................................................................... 45

8.3.4 LVDS Input / Output Port ................................................................................................................................................................. 46

8.3.4.1 LVDS Input Port ............................................................................................................................................................... 46

8.3.4.2 LVDS Output Port ............................................................................................................................................................. 47

8.3.5 Output Clock Duty Cycle .................................................................................................................................................................. 48

8.3.6 Wiring the Differential Input for Single-Ended Levels ....................................................................................................................... 49

JITTER PERFORMANCE ........................................................................................................................................................................... 50

INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................... 61

OUTPUT / OUTPUT CLOCK TIMING ........................................................................................................................................................... 61

7.1

7.2

JUNCTION TEMPERATURE ......................................................................................................................................................................... 39

THERMAL RELEASE PATH .......................................................................................................................................................................... 39

8.4

8.5

8.6

PACKAGE OUTLINE DRAWINGS – PAGE 1........................................................................................................................

PACKAGE OUTLINE DRAWINGS – PAGE 2........................................................................................................................

ORDERING INFORMATION..................................................................................................................................................

REVISION HISTORY .............................................................................................................................................................

August 28, 2017

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