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70V08L20PFGI

Categorystorage    SRAM memory   
File Size178KB,21 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet View All

70V08L20PFGI Online Shopping

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HIGH-SPEED 3.3V
64K x 8 DUAL-PORT
STATIC RAM
Features
70V08L
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V08L
Active: 550mW (typ.)
Standby: 1mW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT70V08 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0-7L
I/O
Control
(1,2)
I/O
Control
I/O
0-7R
(1,2)
BUSY
L
A
15L
A
0L
BUSY
R
64Kx8
MEMORY
ARRAY
70V08
A
15R
A
0R
Address
Decoder
Address
Decoder
A
15L
A
0L
CE
0L
CE
1L
OE
L
R/W
L
SEM
L
(2)
INT
L
NOTES:
1.
BUSY
is an input as a Slave (M/S-V
IL
) and an output when it is a Master (M/S-V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
A
15R
A
0R
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
3740 drw 01
(1)
M/S
MAY 2019
DSC-3740/11
1
©2019 Integrated Device Technology, Inc.
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