CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and
X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
2.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
DC Operating Specifications
Unless otherwise noted, V
DD
= +2.7V to +5.5V, T
A
= -40°C to +85°C, Typical values are @ T
A
= +25°C
and V
DD
= 3.3V
SYMBOL
V
DD
V
BAT
PARAMETER
Main Power Supply
Backup Power Supply
CONDITIONS
MIN
2.7
1.8
TYP
MAX
5.5
5.5
UNIT
V
V
NOTES
Electrical Specifications
SYMBOL
I
DD1
PARAMETER
Supply Current with I
2
C Active
CONDITIONS
V
DD
= 2.7V
V
DD
= 5.5V
I
DD2
Supply Current for Non-Volatile
Programming
Supply Current for Main
Timekeeping (Low Power Mode)
Battery Supply Current
V
DD
= 2.7V
V
DD
= 5.5V
V
DD
= V
SDA
= V
SCL
= 2.7V
V
DD
= V
SDA
= V
SCL
= 5.5V
V
BAT
= 1.8V,
V
DD
= V
SDA
= V
SCL
= V
RESET
= 0
V
BAT
= 3.0V,
V
DD
= V
SDA
= V
SCL
= V
RESET
= 0
I
BATLKG
V
TRIP
V
TRIPHYS
V
BATHYS
V
DD SR-
IRQ/F
OUT
V
OL
Output Low Voltage
V
DD
= 5V
I
OL
= 3mA
V
DD
= 1.8V
I
OL
= 1mA
I
LO
Output Leakage Current
V
DD
= 5.5V
V
OUT
= 5.5V
100
0.4
0.4
400
V
V
nA
Battery Input Leakage
V
BAT
Mode Threshold
V
TRIP
Hysteresis
V
BAT
Hysteresis
V
DD
Negative Slew Rate
V
DD
= 5.5V, V
BAT
= 1.8V
1.8
2.2
30
50
10
800
850
MIN
TYP
MAX
500
800
2.5
3.5
10
20
1000
1200
100
2.6
UNIT
µA
µA
mA
mA
µA
µA
nA
nA
nA
V
mV
mV
V/ms
7
7, 10
7, 10
8
3, 6, 7
5
3, 4, 5
NOTES
3, 4, 5
I
DD3
I
BAT
3
FN8231.5
October 23, 2006
ISL12026
EEPROM Specifications
SYMBOL
PARAMETER
EEPROM Endurance
EEPROM Retention
Temperature
≤75°C
TEST CONDITIONS
MIN
>2,000,000
50
TYP
MAX
UNITS
Cycles
Years
NOTES
Serial Interface (I
2
C) Specifications
DC Electrical Specifications
SYMBOL
V
IL
V
IH
PARAMETER
SDA, and SCL Input Buffer LOW
Voltage
SDA, and SCL Input Buffer HIGH
Voltage
TEST CONDITIONS
MIN
-0.3
0.7 x V
DD
0.05 x V
DD
I
OL
= 4mA
V
IN
= 5.5V
V
IN
= 5.5V
0
100
100
0.4
TYP
MAX
0.3 x V
DD
V
DD
+ 0.3
UNITS
V
V
V
V
nA
nA
NOTES
Hysteresis SDA and SCL Input Buffer
Hysteresis
V
OL
I
LI
I
LO
SDA Output Buffer LOW Voltage
Input Leakage Current on SCL
I/O Leakage Current on SDA
AC Electrical Specifications
SYMBOL
f
SCL
t
IN
t
AA
PARAMETER
SCL Frequency
Pulse width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Any pulse narrower than the max
spec is suppressed.
SCL falling edge crossing 30% of
V
DD
, until SDA exits the 30% to
70% of V
DD
window.
SDA crossing 70% of V
DD
during
a STOP condition, to SDA
crossing 70% of V
DD
during the
following START condition.
Measured at the 30% of V
DD
crossing.
Measured at the 70% of V
DD
crossing.
SCL rising edge to SDA falling
edge. Both crossing 70% of V
DD
.
From SDA falling edge crossing
30% of V
DD
to SCL falling edge
crossing 70% of V
DD
.
From SDA exiting the 30% to
70% of V
DD
window, to SCL rising
edge crossing 30% of V
DD
.
From SCL rising edge crossing
70% of V
DD
to SDA entering the
30% to 70% of V
DD
window.
From SCL rising edge crossing
70% of V
DD
, to SDA rising edge
crossing 30% of V
DD
.
1300
TEST CONDITIONS
MIN
TYP
MAX
400
50
900
UNITS
kHz
ns
ns
NOTES
t
BUF
ns
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
1300
600
600
600
ns
ns
ns
ns
t
SU:DAT
Input Data Setup Time
100
ns
t
HD:DAT
Input Data Hold Time
0
ns
t
SU:STO
STOP Condition Setup Time
600
ns
4
FN8231.5
October 23, 2006
ISL12026
AC Electrical Specifications
SYMBOL
t
HD:STO
PARAMETER
STOP Condition Hold Time for
Read, or Volatile Only Write
Output Data Hold Time
(Continued)
TEST CONDITIONS
From SDA rising edge to SCL
falling edge. Both crossing 70%
of V
DD
.
From SCL falling edge crossing
30% of V
DD
, until SDA enters the
30% to 70% of V
DD
window.
MIN
600
TYP
MAX
UNITS
ns
NOTES
t
DH
0
ns
Cb
Cpin
t
WC
NOTES:
Capacitive Loading of SDA or SCL Total on-chip and off-chip.
SDA, and SCL Pin Capacitance
Non-volatile Write Cycle Time
10
400
10
12
20
pF
pF
ms
10
3. IRQ/F
OUT
Inactive.
4. V
IL
= V
DD
x 0.1, V
IH
= V
DD
x 0.9, f
SCL
= 400kHz
5. V
DD
> V
BAT
+V
BATHYS
6. Bit BSW = 0 (Standard Mode), V
BAT
>= 1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
9. Parameter is not 100% tested.
10. t
WC
is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
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