Preliminary Datasheet
LP1113
Dual Bootstrapped, 12V MOSFET Driver with Output Disable
General Description
The LP1113 is a single phase 12V MOSFET gate
driver optimized to drive the gates of both high-side
and low-side power MOSFETs in a synchronous buck
converter.
With a wide operating voltage range, high or low side
MOSFET gate drive voltage can be optimized for the
best efficiency. Internal adaptive non-overlap circuitry
further reduces
switching
losses by preventing
simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST
voltages as high as 35V, with transient voltages as
high as 40V. Both gate outputs can be driven low by
applying a low logic level to the enable(EN) pin. An
undervoltage lockout function ensures that both driver
outputs are low when the supply voltage is low, and a
Thermal Shutdown function provides the IC with
over-temperature protection.
C1
VCC
Features
All-In-One Synchronous Buck Driver
Bootstrapped High-Side Drive
One PWM Signal Generates Both Drives
Anti-cross Conduction Protection Circuitry
Available in MSOP-10 Package
Applications
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Typical Application Circuit
VIN
VCC
D1
C2
C3
M1
LP1113
BST
DRVH
EN
SWN
DRVL
PWM
PGND
L1
EN
VOUT
Order Information
LP1113
□ □
□
F: Halogen Free & Pb Free
Package Type
MS: MSOP-10
PWM
M2
C4
Marking Information
Device
LP1113
Marking
LPS
LP1113
YWX
Y:Production year
W:Production period X:Production batch
Package
MSOP-10
Shipping
3K/REEL
LP1113-00
Oct.-2017
Email:
marketing@lowpowersemi.com
www.lowpowersemi.com
Page 1 of 8
Preliminary Datasheet
Functional Pin Description
Package Type
Pin Configurations
LP1113
VCC
BST
1
2
3
4
5
MSOP-10
TOP VIEW
10
9
8
7
6
DRVL
PGND
PWM
EN
NC
MSOP-10
DVRH
SWN
NC
Pin
1
Name
VCC
Description
Input Supply. A 1.0μF ceramic capacitor should be connected from this pin to PGND.
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and
SW pins holds this bootstrap voltage for the high-side MOSFET as it is switched. The
recommended capacitor value is between 100nF and 1.0μF. An external diode is
required with the LP1113.
Output drive for the upper MOSFET.
Switch Node. Connect to the source of the upper MOSFET.
No Connect.
No Connect.
2
BST
3
4
5
6
7
8
9
10
DRVH
SWN
NC
NC
EN
PWM
PGND
DRVL
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
Logic-Level Input. This pin has primary control of the drive outputs.
Power Ground. Should be closely connected to the source of the lower MOSFET.
Output drive for the lower MOSFET.
LP1113-00
Oct.-2017
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Page 2 of 8
Preliminary Datasheet
Function Diagram
BST
LP1113
DRVH
SWN
LOGIC
Anti-Cross
Conduction
VCC
UVLO
PWM
EN
VCC
DRVL
OTP
PGND
Timing Diagram
EN
V
EN_LO
DRVH or DRVL
T
pdlEN
90%
10%
V
EN_HI
T
pdhEN
Figure 1.
V
PWM_HI
PWM
DRVL
T
pdlDRVL
T
fDRVL
90%
2V
10%
EN Timing waveforms
V
PWM_LO
90%
10%
T
pdhDRVH
T
rDRVH
DRVH-SWN
10%
90%
T
pdlDRVH
90%
T
fDRVH
T
rDRVL
2V
10%
T
pdhDRVL
SWN
Figure 2.
Input-Output Timing waveforms
LP1113-00
Oct.-2017
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Page 3 of 8
Preliminary Datasheet
Absolute Maximum Ratings
LP1113
VCC ------------------------------------------------------------------------------------------------------------------ -0.3V to 15V
BST
---------------------------------------------------------------------------------------------------------------- -0.3V to 35V
BST to SWN ------------------------------------------------------------------------------------------------------- -0.3V to 15V
SWN --------------------------------------------------------------------------------------------------------------------- -5V to 20V
DRVH ----------------------------------------------------------------------------------------------- SWN-0.3V to BST+0.3V
DRVL ------------------------------------------------------------------------------------------------------- -0.3V to VCC+0.3V
EN,PWM ----------------------------------------------------------------------------------------------------------- -0.3V to 6.5V
Maximum Junction Temperature ------------------------------------------------------------------------------------ 150℃
Maximum Soldering Temperature (at leads,10 sec) ----------------------------------------------------------- 260℃
Storage Temperature --------------------------------------------------------------------------------------- -55℃ to 150℃
Operating Ambient Temperature Range
-------------------------------------------------------------- -40℃
to
85℃
Note1：All voltages are with respect to PGND except where noted.
Note2：Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note3: This device is ESD sensitive. Use standard ESD precautions when handling.
Thermal Information
Package Thermal Resistance (
Note4
)
Maximum Power Dissipation (PD,T
A
=25℃) ----------------------------------------------------------------------- 1.0W
Junction to Ambient,
θ
JA
--------------------------------------------------------------------------------------------- 125℃/W
Note4：2 layer board, 1 in2 Cu, 1 oz thickness.
LP1113-00
Oct.-2017
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Page 4 of 8
Preliminary Datasheet
Electrical Characteristics
(VCC = 12 V, TA =25°C, unless otherwise noted.)
Characteristic
Supply
Supply Voltage Range
Supply Current
EN Input
Input Voltage High
Input Voltage Low
Hysteresis
Input Current
PWM Input
Input Voltage High
Input Voltage Low
Hysteresis
Input Current
High-Side Driver
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
−
−
−
trDRVH
tfDRVH
tpdhDRVH
Propagation Delay Times
tpdlDRVH
tpdlEN
tpdhEN
SW Pulldown Resitance
Low-Side Driver
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
−
−
−
trDRVL
tfDRVL
tpdhDRVL
Propagation Delay Times
tpdlDRVL
tpdlEN
tpdhEN
Timeout Delay
Under Voltage Lockout
UVLO Startup
UVLO Shutdown
Hysteresis
−
−
−
−
−
−
-
-
-
4.3
4.0
0.3
−
VCC = PGND
CLOAD = 3.0 nF, (See Figure 2)
CLOAD = 3.0 nF, (See Figure 2) (Note 5, tpdhDRVL only)
(See Figure 1)
(See Figure 1)
DRVH
−
SWN = 0
−
−
−
−
−
-
-
-
−
3.3
0.5
15
30
12
105
15
30
35
110
−
BST
−
SWN = 12 V
BST
−
SWN = 12 V
BST
−
SWN = 0 V
BST
−
SWN = 12 V, CLOAD = 3.0 nF (See Figure 2)
BST
−
SWN = 12 V, CLOAD = 3.0 nF (See Figure 2)
BST
−
SWN = 12 V, CLOAD = 3.0 nF (See Figure 2)
(See Figure 1)
(See Figure 1)
SWN to PGND
−
−
−
−
−
-
3.3
0.5
15
30
12
95
15
30
35
15
VPWM_HI
VPWM_LO
−
−
−
−
−
No internal pull-up or pull-down resistors
2.0
−
−
−1.0
−
−
300
−
VEN_HI
VEN_LO
−
−
−
No internal pull-up or pull-down resistors
2.0
−
−
−1.0
−
−
300
−
VCC
ISYS
−
BST = 12 V, IN = 0 V, EN=0V
4.4
−
−
0.7
Symbol
Condition
Min
Typ
LP1113
Max
13.2
−
−
0.8
−
+1.0
−
0.8
−
+1.0
-
-
-
-
-
-
-
-
-
−
-
−
−
-
-
-
-
-
-
−
-
-
-
Unit
V
mA
V
V
mV
μA
V
V
mV
μA
Ω
Ω
kΩ
ns
ns
ns
ns
ns
ns
kΩ
Ω
Ω
kΩ
ns
ns
ns
ns
ns
ns
ns
V
V
V
Note5: Guaranteed by design; not tested in production.
LP1113-00
Oct.-2017
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www.lowpowersemi.com
Page 5 of 8
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