MCP2517FD
External CAN FD Controller with SPI Interface
Features
General
External CAN FD Controller with SPI Interface
Arbitration Bit Rate up to 1 Mbps
Data Bit Rate up to 8 Mbps
CAN FD Controller modes
- Mixed CAN 2.0B and CAN FD mode
- CAN 2.0B mode
• Conforms to ISO11898-1:2015
Message FIFOs
• 31 FIFOs, configurable as transmit or receive
FIFOs
• One Transmit Queue (TXQ)
• Transmit Event FIFO (TEF) with 32 bit time stamp
Message Transmission
• Message transmission prioritization:
- Based on priority bit field, and/or
- Message with lowest ID gets transmitted first
using the Transmit Queue (TXQ)
• Programmable automatic retransmission
attempts: unlimited, 3 attempts or disabled
Message Reception
• 32 Flexible Filter and Mask Objects
• Each object can be configured to filter either:
- Standard ID + first 18 data bits, or
- Extended ID
• 32-bit Time Stamp
Special Features
• VDD: 2.7 to 5.5V
• Active current: max. 12 mA @5.5 V, 40 MHz CAN
clock
• Sleep current: 10 µA, typical
• Message objects are located in RAM: 2 KB
• Up to 3 configurable interrupt pins
• Bus Health Diagnostics and Error counters
• Transceiver standby control
• Start of frame pin for indicating the beginning of
messages on the bus
• Temperature ranges:
- High (H): –40°C to +150°C
TXCAN
RXCAN
CLKO/SOF
INT
OSC2
OSC1
VSS
1
2
3
4
5
6
7
Oscillator Options
• 40, 20 or 4 MHz crystal, or ceramic resonator; or
external clock input
• Clock output with prescaler
SPI Interface
• Up to 20 MHz SPI clock speed
• Supports SPI modes 0,0 and 1,1
• Registers and bit fields are arranged in a way to
enable efficient access via SPI
Safety Critical Systems
• SPI commands with CRC to detect noise on SPI
interface
• Error Correction Code (ECC) protected RAM
Additional Features
• GPIO pins: INT0 and INT1 can be configured as
general purpose I/O
• Open drain outputs: TXCAN, INT, INT0, and INT1
pins can be configured as push/pull or open drain
outputs
•
•
•
•
Package Types
MCP2517FD
SOIC14
14
13
12
11
10
9
8
VDD
nCS
SDO
SDI
SCK
INT0/GPIO0/XSTBY
INT1/GPIO1
MCP2517FD
VDFN14 with wettable flanks*
TXCAN
RXCAN
CLKO/SOF
INT
OSC2
OSC1
VSS
1
2
3
4
5
6
7
EP*
14
13
12
11
10
9
8
VDD
nCS
SDO
SDI
SCK
INT0/GPIO0/XSTBY
INT1/GPIO1
DFN14 includes an Exposed Thermal Pad (EP); see
Table 1-1
2017 Microchip Technology Inc.
DS20005688A-page 1
MCP2517FD
1.0
DEVICE OVERVIEW
1.1
Block Diagram
The
MCP2517FD
is
a
cost-effective
and
small-footprint CAN FD controller that can be easily
added to a microcontroller with an available SPI
interface. Therefore, a CAN FD channel can be easily
added to a microcontroller that is either lacking a CAN
FD peripheral, or that doesn’t have enough CAN FD
channels.
The MCP2517FD supports both, CAN frames in the
Classical format (CAN2.0B) and CAN Flexible Data
Rate (CAN FD) format, as specified in ISO11898-
1:2015.
Figure 1.1
shows the block diagram of the
MCP2517FD. The MCP2517FD contains the following
main blocks:
• The CAN FD Controller module implements the
CAN FD protocol and contains the FIFOs, and Fil-
ters.
• The SPI interface is used to control the device by
accessing SFRs and RAM.
• The RAM controller arbitrates the RAM accesses
between the SPI and CAN FD Controller module.
• The Message RAM is used to store the data of the
Message Objects.
• The oscillator generates the CAN clock.
• The Internal LDO and POR circuit.
• The I/O control.
Note 1:
This data sheet summarizes the features
of the MCP2517FD. It is not intended to
be a comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“MCP2517FD
Family
Reference
Manual”.
FIGURE 1-1:
VDD
MCP2517FD BLOCK DIAGRAM
nCS
SPI
Interface
SCK
SDI
SDO
Internal
LDO
VSS
POR
CLKO/SOF
Message
RAM
RAM
Controller
I/O
INT
INT0/GPIO0/XSTBY
OSC1
Oscillator
CAN FD
Controller
Module
INT1/GPIO1
OSC2
RX
Filter
RXCAN
TXCAN
DS20005688A-page 2
2017 Microchip Technology Inc.
MCP2517FD
1.2
Pin Out Description
MCP2517FD STANDARD PINOUT VERSION
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
-
VDFN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin Type
O
I
O
O
O
I
P
I/O
I/O
I
I
O
I
P
P
Description
Transmit output to CAN FD transceiver
Receive input from CAN FD transceiver
Clock output/Start of Frame output
Interrupt output (active low)
External oscillator output
External oscillator input
Ground
RX Interrupt output (active low)/GPIO
TX Interrupt output (active low)/GPIO/
Transceiver Standby output
SPI clock input
SPI data input
SPI data output
SPI chip select input
Positive Supply
Exposed Pad; connect to VSS
Table 1-1
describes the functions of the pins.
TABLE 1-1:
Pin Name
TXCAN
RXCAN
CLKO/SOF
INT
OSC2
OSC1
VSS
INT1/GPIO1
INT0/GPIO0/
XSTBY
SCK
SDI
SDO
nCS
VDD
EP
Legend:
P = Power, I = Input, O = Output
2017 Microchip Technology Inc.
DS20005688A-page 3
MCP2517FD
1.3
Typical Application
Figure 1-2
shows an example of a typical application
of the MCP2517FD. In this example, the microcontrol-
ler operates at 3.3V.
The MCP2517FD interfaces directly with microcontrollers
operating at 2.7V to 5.5V. In addition, the MCP2517FD
connects directly to high-speed CAN FD transceivers.
There are no external level shifters required when
connecting V
DD
of the MCP2517FD and the
microcontroller to VIO of the transceiver.
The V
DD
of the CAN FD transceiver is connected to
5V.
The SPI interface is used to configure and control the
CAN FD controller.
The MCP2517FD signals interrupts to the microcon-
troller using INT, INT0 and INT1. Interrupts need to be
cleared by the microcontroller through SPI.
The CLKO pin
microcontroller.
provides
the
clock
to
the
FIGURE 1-2:
VBAT
MCP2517FD INTERFACING WITH A 3.3V MICROCONTROLLER
5V LDO
3.3V LDO
0.1
μF
0.1
μF
0.1
μF
0.1 μF
CANH
VDD
RA0
SCK
SDO
nCS
SCK
SI
SO
INT
INT0
INT1
CLKO
VDD
TXCAN
RXCAN
VIO
TXD
RXD
STBY
VSS
VDD
CANH
120
CANL
PIC®
SDI
INT0
INT1
INT2
OSC1
MCP2517FD
CANL
OSC2
22 pF
OSC1
VSS
22 pF
VSS
DS20005688A-page 4
2017 Microchip Technology Inc.
MCP2517FD
2.0
CAN FD CONTROLLER
MODULE
• Each FIFO can be configured either as a Transmit
or Receive FIFO. The FIFO Control keeps track of
the FIFO Head and Tail, and calculates the User
Address. For a TX FIFO, the User Address points
to the address in RAM where the data for the next
transmit message shall be stored. For a RX FIFO,
the User Address points to the address in RAM
where the data of the next receive message shall
be read. The User notifies the FIFO that a
message was written to or read from RAM by
incrementing the Head/Tail of the FIFO.
• The Transmit Queue (TXQ) is a special transmit
FIFO that transmits the messages based on the
ID of the messages stored in the queue.
• The Transmit Event FIFO (TEF) stores the
message IDs of the transmitted messages.
• A free-running Time Base Counter is used to time
stamp received messages. Messages in the TEF
can also be time stamped.
• The CAN FD Controller module generates
interrupts when new messages are received or
when messages were transmitted successfully.
• The Special Function Registers (SFR) are used to
control and to read the status of the CAN FD
Controller module.
Note 1:
This data sheet summarizes the features
of the CAN FD Controller module. It is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
related section of the “MCP2517FD
Family Reference Manual”.
Figure 2-1
shows the main blocks of the CAN FD
Controller module:
• The CAN FD Controller module has multiple
modes:
- Configuration
- Normal CAN FD
- Normal CAN 2.0
- Sleep
- Listen Only
- Restricted Operation
- Internal and External Loop back modes
• The CAN FD Bit Stream Processor (BSP)
implements the Medium Access Control of the
CAN FD protocol described in ISO11898-1:2015.
It serializes and de-serializes the bit stream,
encodes and decodes the CAN FD frames,
manages the medium access, acknowledges
frames, and detects and signals errors.
• The TX Handler prioritizes the messages that are
requested for transmission by the Transmit
FIFOs. It uses the RAM Interface to fetch the
transmit data from RAM and provides it to the
BSP for transmission.
• The BSP provides received messages to the RX
Handler. The RX Handler uses the Acceptance
Filter to filter out messages that shall be stored
into Receive FIFOs. It uses the RAM Interface to
store received data into RAM.
FIGURE 2-1:
CAN FD CONTROLLER MODULE BLOCK DIAGRAM
Mode
Control
SFR
Time Stamping
TBC
RAM
Interface
FIFO
Control
TXQ Control
TX Handler
TX Prioritization
RX Handler
Acceptance
Filter
CAN FD
Protocol
Bit Stream
Processor
TEF
Control
Interrupt
Control
Error
Handling
Diagnostics
2017 Microchip Technology Inc.
DS20005688A-page 5
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