MIC24046
Pin-Programmable, 4.5V
−
19V, 5A
Step-Down Converter
General Description
The MIC24046 is a pin-programmable, high–efficiency,
wide input range, 5A synchronous step-down regulator.
The MIC24046 is perfectly suited for multiple-voltage rail
application environments typically found in computing and
telecommunication systems. It can be programmed by pin
strapping various parameters, such as output voltage,
switching frequency, and current-limit values. The pin-
selectable switching frequency, valley-current mode
control technique, high–performance error amplifier, and
external compensation allow for the best trade-offs
between high efficiency and the smallest possible solution
size.
The MIC24046 is available in a thermally–efficient, space-
saving, 20–pin 3mm × 3mm QFN package with an
operating junction temperature range of –40°C to +125°C.
Datasheets and support documentation are available on
Micrel’s website at:
www.micrel.com.
Features
•
•
•
•
4.5V to 19V input voltage range
5A (maximum) output current
High efficiency (>90%)
Pin-selectable output voltages:
−
0.7V, 0.8V, 0.9V, 1.0V, 1.2V, 1.5V, 1.8V,
2.5V, and 3.3V
±1% output voltage accuracy
Supports safe start-up with pre-biased output
Pin-selectable current limit and switching frequency
Internal soft-start and thermal shutdown protection
Hiccup-mode short-circuit protection
Available in a 20-pin 3mm × 3mm QFN package
–40°C to +125°C junction temperature range
•
•
•
•
•
•
•
Applications
•
Servers, data storage, routers, and base stations
•
FPGAs, DSP, and low-voltage ASIC power
Typical Application
MIC24046 12V
IN
5A DC/DC Converter
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
October 14, 2015
Revision 1.1
Micrel, Inc.
MIC24046
Ordering Information
Part Number
MIC24046YFL
Junction Temperature Range
–40°C to +125°C
Package
20–Pin 3mm × 3mm QFN
Lead Finish
Pb-Free
Pin Configuration
20–Pin 3mm × 3mm QFN (FL)
(Top View)
Pin Description
Pin Number
1
−
2
Pin Name
Pin Function
Input Voltage for the Buck Converter Power Stage: These pins are the drain terminal of the internal
high-side N-channel MOSFET. A 10 µF minimum ceramic capacitor should be connected from VIN to
PGND as close as possible to the device. A combination of multiple ceramic capacitors of different
sizes is recommended.
Low-Side MOSFET Source Terminal and Low-Side Driver Return: Connect the ceramic input
capacitors to PGND as close as possible to the device.
Switch Node: Drain (low-side MOSFET) and source (high-side MOSFET) connection of the internal
power N-channel FETs. The external inductor (switched side) and bootstrap capacitor (bottom
terminal) must be connected to these pins.
Bootstrap: Supply voltage for the driver of the high-side N-channel power MOSFET. Connect the
bootstrap capacitor (top terminal) to this pin.
Power Good (Output): When the output voltage is within 92.5% of the nominal set point, this pin will
go from logic low to logic high through an external pull-up resistor. This pin is the drain connection of
an internal N-channel FET.
Three-state Pin (Low, High, and High-Z) for Output Voltage Programming: Together with VOSET1,
VOSET0 defines nine logic values corresponding to nine output voltage selections.
Three-State Pin (Low, High, and High-Z) for Output Voltage Programming: Together with VOSET0,
VOSET1 defines nine logic values corresponding to nine output voltage selections.
VIN
3
−
4, 13
5
−
6
PGND
LX
7
BST
8
PG
9
10
VOSET0
VOSET1
October 14, 2015
2
Revision 1.1
Micrel, Inc.
MIC24046
Pin Description (Continued)
Pin Number
11
12
14
15
16
Pin Name
ILIM
FREQ
AGND
COMP
OUTSNS
Pin Function
Three-State (Low, High, and High-Z) Current-Limit Selection Pin.
Three-State (Low, High, and High-Z) Switching Frequency Selection Pin.
Analog Ground: Quiet ground for the analog circuitry of the internal regulator and return terminal for
the external compensation network.
Transconductance Error Amplifier Output: Connect a compensation network from this pin to AGND.
Output Sensing: Connect this pin directly to the buck converter output voltage. This pin is the top side
terminal of the internal feedback divider.
Precision Enable/Turn-On Delay Input. The EN/DLY pin is first compared against a 507mV threshold
to turn-on the on-board LDO regulator. The EN/DLY pin is then compared against a 1.21V (typical)
threshold to initiate output power delivery. A 150mV typical hysteresis prevents chattering when
power delivery is started. A 2µA (typical) current source pulls up the EN/DLY pin. Turn-on delay can
be achieved by connecting a capacitor from EN/DLY to ground, while using an open-drain output to
drive the EN/DLY pin.
Output of the internal linear regulator and internal supply for analog control. A 1µF minimum ceramic
capacitor should be connected from this pin to AGND; 2.2µF nominal value recommended.
Internal Supply Rail for the MOSFET Drivers (fed by the VDDA pin): An internal resistor (10Ω)
between pins VDDP and VDDA is provided in the regulator in order to implement an RC filter for
switching noise suppression. A 1µF minimum ceramic capacitor should be connected from this pin to
PGND; 2.2µF nominal value recommended.
Input of the Internal Linear Regulator: This pin is typically connected to the input voltage of the buck
converter stage (VIN). If VINLDO and VIN are connected to different voltage rails, individually bypass
VINLDO to ground with a 100nF ceramic capacitor.
PGND Exposed Pad: Electrically connected to PGND pins. Connect with thermal vias to the ground
plane to ensure adequate heat-sinking. Follow recommendations as illustrated in the
PCB Layout
Recommendations
section
VIN Exposed Pad: Electrically connected to VIN pins. If an input power distribution plane is available,
connect with thermal vias to that plane to improve heat-sinking. Follow recommendations as
illustrated in the
PCB Layout Recommendations
section
LX Exposed Pad: Electrically connected to LX pins. Follow recommendations as illustrated in the
PCB Layout Recommendations
section
17
EN/DLY
18
VDDA
19
VDDP
20
VINLDO
PGND_EP
PGND
VIN_EP
VIN
LX_EP
LX
October 14, 2015
3
Revision 1.1
Micrel, Inc.
MIC24046
Absolute Maximum Ratings
(1)
V
VIN
, V
VINLDO
to AGND ...................................
−0.3V
to +20V
V
VDDP
, V
VDDA
to AGND .....................................
−0.3V
to +6V
V
VINLDO
to V
VDDA
.............................................
−0.3V
to +20V
V
VDDP
to V
VDDA
...............................................
−0.3V
to +0.3V
V
VOSETx
, V
FREQ
, V
ILIM
, to AGND .........................
−0.3V
to +6V
V
BST
to V
LX
.......................................................
−0.3V
to +6V
V
BST
to AGND ................................................
−0.3V
to +26V
V
EN/DLY
to AGND ........................
−0.3V
to V
VDDA
+ 0.3V, +6V
V
PG
to AGND ...................................................
−0.3V
to +6V
V
COMP
, V
OUTSNS
to AGND ...........
−0.3V
to V
VDDA
+ 0.3V, +6V
AGND to PGND............................................
−0.3V
to +0.3V
Junction Temperature .............................................. +150°C
Storage Temperature (T
S
) .........................
−65°C
to +150°C
Lead Temperature (soldering, 10s) ............................ 260°C
(4)
ESD Rating
HBM ......................................................................... 2kV
MM ......................................................................... 150V
Operating Ratings
(2)
Supply Voltage (V
VIN
, V
VINLDO
) ........................... 4.5V to 19V
Externally Applied Analog and Drivers Supply Voltage
(V
VINLDO
= V
VDDA
= V
VDDP
) .................................. 4.5V to 5.5V
Enable Voltage (V
EN/DLY
) .................................... 0V to V
VDDA
Power-Good (PG) Pull-up Voltage (V
PU_PG
) ........ 0V to 5.5V
Output Current ................................................................. 5A
Junction Temperature (T
J
) ........................
−40°C
to +125°C
Junction to Ambient Thermal Resistance
(3)
20-pin 3mm × 3mm QFN (θ
JA
) ........................ 29°C/W
Electrical Characteristics
(5)
V
VIN
= V
VINLDO
= 12V; C
VDDA
= 2.2µF, C
VDDP
= 2.2µF, T
A
= 25°C, unless otherwise noted.
Bold
values indicate
−40°C
≤ T
J
≤ +125°C.
Symbol
VIN Supply
VIN
IVINQ
IVINLDOQ
IVINOp
IVINLDOOp
Input Range
Disable Current
Disable Current
Operating Current
Operating Current
EN/DLY = 0V
EN/DLY = 0V
T
A
= T
J
= 25°C
−40°C
≤ T
J
≤ +125°C
0.45
5.6
4.5
0.2
35
19
2
42
56
0.75
7
V
µA
µA
mA
mA
Parameter
Test Conditions
Min.
Typ.
Max.
Units
EN/DLY > 1.28V, OUTSNS = 1.15 × V
OUT(NOM)
,
no switching, T
A
= T
J
= 25°C
EN/DLY > 1.28V, OUTSNS = 1.15 × V
OUT(NOM)
,
no switching, T
A
= T
J
= 25°C
VDDA 5V Supply
VDDA
Operating Voltage
Dropout Operation
EN/DLY > 0.58V, I
(VDDA)
= 0mA to 10mA
V
INLDO
= 4.5V, EN/DLY > 0.58V, I
(VDDA)
= 10mA
4.8
3.6
5.1
3.75
5.4
V
V
VDDA Undervoltage Lockout
UVLO_R
UVLO_F
UVLO_H
Notes:
1. Exceeding the absolute maximum ratings may damage the device.
2. The device is not guaranteed to function outside operating range.
3.
θ
JA
is measured on the MIC24046 evaluation board.
4. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.
5. Specification for packaged product only.
VDDA UVLO Rising
VDDA UVLO Falling
VDDA UVLO Hysteresis
V
VDDA
Rising, EN/DLY > 1.28V
V
VDDA
Falling, EN/DLY > 1.28V
3.1
2.87
3.5
3.2
300
3.9
3.45
V
V
mV
October 14, 2015
4
Revision 1.1
Micrel, Inc.
MIC24046
Electrical Characteristics
(5)
(Continued)
Symbol
Parameter
V
VIN
= V
VINLDO
= 12V; C
VDDA
= 2.2µF, C
VDDP
= 2.2µF, T
A
= 25°C, unless otherwise noted.
Bold
values indicate
−40°C
≤ T
J
≤ +125°C.
Test Conditions
Min.
Typ.
Max.
Units
EN/DLY Control
EN_LDO_R
EN_LDO_F
EN_LDO_H
EN_R
EN_F
EN_H
EN_I
LDO Enable Threshold
LDO Disable Threshold
LDO Threshold Hysteresis
EN/DLY Rising Threshold
EN/DLY Falling Threshold
EN/DLY Hysteresis
EN/DLY Pull-Up Current
T
A
= T
J
= 25°C
1
Initiates power-stage operation
Stops power-stage operation
1.14
Turns On VDDA LDO
Turns Off VDDA LDO
460
507
491
16
1.21
1.06
150
2
3
1.28
580
mV
mV
mV
V
V
mV
µA
Switching Frequency
f
SZ
f
S0
f
S1
Programmable Frequency
(High Z)
Programmable Frequency 0
Programmable Frequency 1
FREQ = High Z (open)
FREQ = Low (GND)
FREQ = High (VDDA)
360
500
700
400
565
790
440
630
880
kHz
kHz
kHz
Overcurrent Protection
I
LIM_HS0
I
LIM_HS1
I
LIM_HSZ
LEB
I
LIM_LS0
I
LIM_LS1
I
LIM_LSZ
IN
HICC_DE
HS Current Limit 0
HS Current Limit 1
HS Current Limit High Z
Top FET Current-Limit
Leading Edge-Blanking Time
LS Current Limit 0
LS Current Limit 1
LS Current Limit Hi Z
OC Events Count for Hiccup
ILIM = Low (GND)
ILIM = High (VDDA)
ILIM = High Z (Open)
Number of subsequent cycles in
current limit before entering hiccup
overload protection.
Duration of the High-Z state on LX
before new soft-start.
3.0
4.0
5.0
ILIM = Low (GND)
ILIM = High (VDDA)
ILIM = High Z (open)
6.0
8.1
9.3
7.1
9.3
10.5
108
4.6
6.2
6.8
15
3x
Soft-Start
Time
6.3
7.9
8.6
8.1
10.3
11.9
A
A
A
ns
A
A
A
Clock
Cycles
t
HICC_WAIT
Hiccup Wait Time
Power Switches
R
BOTTOM
R
TOP
Bottom FET ON resistance
Top FET ON resistance
V
VIN
= V
VINLDO
= V
VDDP
= V
VDDA
= 5V,
V
BST
-V
LX
= 5V, T
A
= T
J
= 25°C
V
VIN
= V
VINLDO
= V
VDDP
= V
VDDA
= 5V,
V
BST
-V
LX
= 5V, T
A
= T
J
= 25°C
16
38
21
50
mΩ
mΩ
Pulse-Width Modulation (PWM)
T
ON(MIN)
Minimum LX ON Time
T
A
= T
J
= 25°C
V
VIN
= V
VINLDO
= V
VDDA
= 5V, V
OUTSNS
=
3V, FREQ = Open (400kHz setting),
V
VOSET0
= V
VOSET1
= 0V (3.3V
setting),T
A
= T
J
= 25°C
V
OUTSNS
>1.1 × V
OUT(NOM)
26
ns
T
OFF(MIN)
Minimum LX OFF time
90
135
190
ns
D
MIN
Minimum Duty Cycle
0
%
October 14, 2015
5
Revision 1.1
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