SY89858U
Precision Low Power 1:8 LVPECL
Fanout Buffer with Internal Termination
General Description
The SY89858U is a 2.5V/3.3V precision, high-
speed, fully differential LVPECL 1:8 fanout buffer
optimized to provide eight identical output copies
with less than 30ps of skew and less than 10ps
pp
total jitter. It can process clock signals as fast as
2.0GHz.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that allows the
SY89858U to directly interface to LVPECL, CML,
and LVDS differential signals (AC- or DC-coupled)
as small as 100mV without any level shifting or
termination resistor networks in the signal path. The
result is a clean, stub-free, low-jitter interface
solution.
The
LVPECL
(100k
temperature
compensated) outputs feature 800mV typical swing
into 50Ω loads, and provide fast rise/fall times
guaranteed to be less than 200ps.
The SY89858U operates from a 2.5V ±5% supply or
3.3V ±10% supply and is guaranteed over the full
industrial temperature range of –40°C to +85°C. For
applications that require a higher speed fanout
buffer, consider the SY58032U. The SY89858U is
®
part of Micrel’s high-speed, Precision Edge product
line. All support documentation can be found on
Micrel’s web site at: www.micrel.com.
Precision Edge
®
Features
Precision 1:8, LVPECL fanout buffer
Low power: 238mW (2.5V)
Guaranteed AC performance over temperature
and supply voltage:
– Wide operating frequency: DC to 2.0GHz
– <380ps In-to-Out t
pd
– <200ps t
r
/t
f
– <30ps skew
Ultra-low jitter design:
– 710fs RMS phase jitter (Typ)
100k LVPECL compatible outputs
Fully differential inputs/outputs
Accepts an input signal as low as 100mV
(200mV
pp
)
Unique patent pending input termination and VT
pin accepts DC-coupled and AC-coupled
differential inputs (LVPECL, LVDS, and CML)
Power supply 2.5V ±5% or 3.3V ±10%
-40°C to +85°C industrial temperature range
Available in 32-pin (5mm x 5mm) QFN package
Applications
All SONET and GigE clock distribution
All Fibre Channel clock and data distribution
Network routing engine timing distribution
High-end, low-skew multiprocessor synchronous
clock distribution
Markets
LAN/WAN
Enterprise servers
ATE
Test and measurement
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
Oct. 1, 2013
M9999-082907-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89858U
Typical Application
Oct. 1, 2013
2
M9999-082907-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89858U
Ordering Information
(1)
Part Number
SY89858UMG
SY89858UMGTR
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals Only.
2. Tape and Reel.
(2)
Package
Type
QFN-32
QFN-32
Operating
Range
Industrial
Industrial
Package Marking
SY89858 with Pb-Free bar-line indicator
SY89858 with Pb-Free bar-line indicator
Lead
Finish
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Pin Configuration
32-Pin QFN
Pin Description
Pin Number
3, 6
Pin Name
IN, /IN
Pin Function
Differential Input: This differential input accepts AC- or DC-coupled signals as
small as 100mV (200mV
PP
). Each pin of this pair internally terminates to a VT pin
open. Please refer to the “Input Interface Applications” section for more details.
4
VT
Input Termination Center-Tap: Each side of the differential input pair terminates
to this VT pin. The VT pin provides a center-tap to a termination network for
maximum interface flexibility. See the “Input Interface Applications” section for
more details.
Reference Voltage: This output biases to V
CC
–1.2V (typical). It is used for AC-
coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT
pin. Bypass with 0.01uF low ESR capacitor to V
CC
. Maximum sink/source
capability is 1.5mA.
Positive Power Su
to the VCC pins as possible.
100k LVPECL Differential Outputs: Differential buffered output copy of the input
signal. The LVPECL output swing is typically 800mV into 50Ω to V
CC
–2V.
Unused output pairs may be left floating with no impact on jitter. See “LVPECL
Output” section.
Ground: Ground pins and exposed pad must be connected to the same ground
plane.
5
1, 8, 9, 16, 18,
23, 25, 32
31, 30, 29, 28,
27, 26, 22, 21,
20, 19, 15, 14,
13, 12, 11, 10
2, 7, 17, 24
VREF-AC
VCC
Q0, /Q0, Q1,
/Q1, Q2, /Q2,
Q3, /Q3, Q4,
/Q4, Q5, /Q5,
Q6, /Q6, Q7,
/Q7
GND
Exposed Pad
Oct. 1, 2013
3
M9999-082907-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89858U
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) .......................... –0.5V to +4.0V
Input Voltage (V
IN
) ..................................–0.5V to V
CC
Termination Current
Source or sink current on V
T
.................. ±100mA
(3)
Reference Current
Source or sink current on V
REF-AC
............ ±1.5mA
LVPECL Output Current (I
OUT
)
Continuous ................................................. 50mA
Surge ........................................................ 100mA
Lead Temperature (soldering, 20 sec.) .......... +260°C
Storage Temperature (T
s
) ..................–65°C to 150°C
Operating Ratings
(2)
Supply Voltage (V
CC
).................. +2.375V to +2.625V
......................................................+3.0V to +3.6V
Ambient Temperature (T
A
) ................ –40°C to +85°C
(4)
Package Thermal Resistance
QFN (
JA
)
Still-Air ..................................................... 35°C/W
QFN (
JB
)
Junction-to-Board .................................... 20°C/W
DC Electrical Characteristics
(5)
T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
CC
I
CC
R
IN
R
DIFF_IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
T_IN
V
REF-AC
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
JA
and
JB
values are determined for a 4-layer board in still air, unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6.
V
IH
(min) not lower than 1.2V.
Parameter
Power Supply
Power Supply Current
Input Resistance
(IN-to-V
T
)
Differential Input Resistance
(IN-to-/IN)
Input High Voltage
(IN, /IN)
Input Low Voltage
(IN, /IN)
Input Voltage Swing
(IN, /IN)
Differential Input Voltage Swing
|IN-/IN|
IN-to-V
T
(IN, /IN)
Output Reference Voltage
Condition
Min
2.375
3.0
Typ
2.5
3.3
95
Max
2.625
3.6
150
55
110
V
CC
V
IH
–0.1
1.7
Units
V
V
mA
Ω
Ω
V
V
V
V
No load, max. V
CC
45
90
Note 6
V
CC
–1.6
0
See Figure 1a.
See Figure 1b.
0.1
0.2
50
100
1.28
V
CC
–1.3V
V
CC
–1.2V
V
CC
–1.1V
V
V
Oct. 1, 2013
4
M9999-082907-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89858U
LVPECL Outputs DC Electrical Characteristics
(7)
V
CC
= 2.5V ±5% or 3.3V ±10%; T
A
= –40°C to + 85°C; R
L
= 50Ω to V
CC
–2V, unless otherwise stated.
Symbol
V
OH
V
OL
V
OUT
V
DIFF-OUT
Note:
7.
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter
Output HIGH Voltage
Q, /Q
Output LOW Voltage
Q, /Q
Output Voltage Swing
Q, /Q
Differential Output Voltage Swing
Q, /Q
Condition
Min
V
CC
–1.145
V
CC
–1.945
Typ
Max
V
CC
–0.895
V
CC
–1.695
Units
V
V
mV
mV
See Figure 1a.
See Figure 1b.
500
1000
800
1600
AC Electrical Characteristics
(8)
V
CC
= 2.5V ±5% or 3.3V ±10%; T
A
= –40°C to + 85°C, R
L
= 50Ω to V
CC
–2V, unless otherwise stated.
Symbol
f
MAX
t
PD
T
pd
Tempco
T
skew
t
Jitter
t
R,
t
F
Notes:
8.
9.
High-frequency AC-parameters are guaranteed by design and characterization.
Output-to-output skew is measured between outputs under identical conditions.
Parameter
Maximum Operating Frequency
Propagation Delay (IN-to-Q)
Differential Propagation Delay
Temperature Coefficient
Output-to-Output Skew
Part-to-Part Skew
RMS Phase Jitter
Output Rise/Fall Time
(20% to 80%)
Condition
V
OUT
≥ 400mV
Min
2.0
180
Typ
3.0
260
115
Max
380
Units
GHz
ps
fs/ C
o
Note 9
Note 10
Output = 25MHz
Integration Range 12kHz – 20MHz
At full output swing.
75
710
130
30
150
ps
fs
200
ps
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs. Part-to-part skew includes variation in t
pd
.
Oct. 1, 2013
5
M9999-082907-C
hbwhelp@micrel.com
or (408) 955-1690
京公网安备 11010802033920号
EEWORLD
