Micrel, Inc.
Precision Edge
2.5V/3.3V TWO INPUT, 1GHz LVTTL/CMOS-
SY89834U
Precision Edge
®
TO-LVPECL 1:4 FANOUT BUFFER/
SY89834U
TRANSLATOR WITH 2:1 INPUT MUX
®
FEATURES
s
Selects between two LVTTL/CMOS inputs and
provides 4 LVPECL output copies
s
Guaranteed AC performance over temperature
and voltage:
• DC-to >1.0GHz throughput
• <500ps propagation delay (IN-to-Q)
• < 20ps within-device skew
• < 225ps rise/fall time
s
Ultra-low jitter design:
• < 1ps
RMS
cycle-to-cycle jitter
• < 1ps
RMS
random jitter
• < 10ps
PP
deterministic jitter
• < 10ps
PP
total jitter (clock)
s
s
s
s
Low voltage 2.5V and 3.3V supply operation
100K LVPECL outputs
Industrial temperature range: –40
°
C to +85
°
C
Includes a 2:1 MUX select input
Precision Edge
®
DESCRIPTION
The SY89834U is a high-speed, 1GHz LVTTL/CMOS-to-
LVPECL fanout buffer/translator optimized for high-speed
ultra-low skew applications. The input stage is designed to
accept two single-ended LVTTL/CMOS compatible signals
that feed into a 2:1 MUX. The selected input is translated
and distributed as four differential 100K LVPECL outputs.
Within device skew is guaranteed to be less than 20ps over
supply voltage and temperature.
The single-ended input buffers accept TTL/CMOS logic
levels. The internal threshold of the buffers is defined as
V
CC
/2
.
The SY89834U is a part of Micrel's high-speed Precision
Edge
®
family. For applications that require a different I/O
combination, consult Micrel's website at: www.micrel.com,
and choose from a comprehensive product line of high-
speed, low-skew fanout buffers, translators and clock
generators.
s
Accepts single-ended TTL/CMOS inputs and
provides four LVPECL outputs
s
Available in 16-pin (3mm
×
3mm) MLF™ package
APPLICATIONS
s
s
s
s
s
Processor clock distribution/translation
SONET clock distribution/translation
Fibre Channel clock distribution/translation
Gigabit Ethernet clock distribution/translation
Single-ended ASIC-to-differential communication
IC signal translation
FUNCTIONAL BLOCK DIAGRAM
1:4
Q0
/Q0
SEL
(LVTTL/CMOS)
Q1
IN1
(LVTTL/CMOS)
/Q1
1
MUX
0
IN2
(LVTTL/CMOS)
EN
LVTTL/CMOS)
D
Q
Q2
/Q2
Q3
/Q3
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame
and MLF are trademarks of Amkor Technology, Inc.
August 2005
1
M9999-080505
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
Precision Edge
®
SY89834U
PACKAGE/ORDERING INFORMATION
VCC
GND
/Q0
Q0
Ordering Information
(1)
12
11
10
9
16
15
14
13
Q1
/Q1
Q2
/Q2
1
2
3
4
5
6
7
8
IN1
SEL
NC
IN2
Part Number
SY89834UMI
SY89834UMITR
(2)
SY89834UMG
(3)
SY89834UMGTR
(2, 3)
Package
Type
MLF-16
MLF-16
MLF-16
MLF-16
Operating
Range
Industrial
Industrial
Industrial
Industrial
Package
Marking
834U
834U
834U with Pb-Free
bar line indicator
834U with Pb-Free
bar line indicator
Lead
Finish
Sn-Pb
Sn-Pb
NiPdAu
Pb-Free
NiPdAu
Pb-Free
/Q3
Q3
VCC
EN
16-Pin MLF™ (MLF-16)
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
PIN DESCRIPTION
Pin Number
15, 16
1, 2,
3, 4,
5, 6
8
Pin Name
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
EN
Pin Function
Differential 100K LVPECL Outputs: These LVPECL outputs are the precision, low skew copies
of the inputs. Please refer to the “Truth Table” section for details. Unused output pairs may be
left open. Terminate wtih 50Ω to V
CC
–2V. See “Output Termination Recommendations” section
for more details.
This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The
synchronous enable ensures that enable/disable will only occur when the outputs are in a logic
LOW state. Note that this input is internally connected to a 25kΩ pull-up resistor and will default
to logic HIGH state (enabled) if left open.
Single-ended TTL/CMOS-compatible inputs to the device. These inputs are internally connected
to a 25kΩ pull-up resistor and will default to logic HIGH state if left open. The input threshold is
V
CC
/2.
No connect. Not internally connected.
TTL/CMOS Compatible Select Input for signals IN1 and IN2. The input threshold is V
CC
/2. HIGH at
the SEL input selects signal IN1. LOW at the SEL input selects signal IN2. SEL includes a 25kΩ
pull-up resistor. The default state is HIGH when left floating.
Ground. GND pins and exposed pad must be connected to the most negative potential of the
device ground.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors and place as close to
each VCC pin as possible.
12,
9
10
11
IN1
IN2
NC
SEL
13
7, 14
GND
VCC
TRUTH TABLE
IN1
0
1
X
X
X
IN2
X
X
0
1
X
EN
1
1
1
1
0
SEL
1
1
0
0
X
Q0–Q3
0
1
0
1
0
(1)
/Q0–Q3
1
0
1
0
0
(1)
Note:
1.
On next negative transition of the input signal (IN).
M9999-080505
hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge
®
SY89834U
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) .................................. –0.5V to +4.0V
Input Voltage (V
IN
) ............................... –0.5V to V
CC
+0.3V
LVPECL Output Current (I
OUT
)
Continuous ............................................................. 50mA
Surge .................................................................... 100mA
Input Current (IN1, IN2) ............................................
±50mA
Lead Temperature (Soldering, 20sec.), ................... 260°C
Storage Temperature (T
S
) ....................... –65°C to +150°C
Operating Ratings
(2)
Supply Voltage Range ........................ +2.375V to +2.625V
............................................................ +3.0V to +3.6V
Ambient Temperature (T
A
) ......................... –40°C to +85°C
Package Thermal Resistance
(3)
MLF™
(θ
JA
)
Still-Air ............................................................. 60°C/W
MLF™
(ψ
JB
)
Junction-to-Board ............................................ 32°C/W
DC ELECTRICAL CHARACTERISTICS
(4)
T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
CC
I
CC
Parameter
Power Supply
Power Supply Current
No load, max. V
CC
.
Condition
Min
2.375
3.0
50
Typ
Max
2.625
3.6
75
Units
V
V
mA
LVTTL/CMOS INPUTS DC ELECTRICAL CHARACTERISTICS
(4)
V
CC
= 2.5V
±5%
or V
CC
= 3.3V
±10%;
T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
I
IH
@ V
IN
= 2.7V
–125
–125
Condition
Min
2.0
0.8
30
Typ
Max
Units
V
V
µA
µA
(100KEP) LVPECL OUTPUTS DC ELECTRICAL CHARACTERISTICS
(4)
V
CC
= 2.5V
±5%
or V
CC
= 3.3V
±10%
, R
L
= 50Ω to V
CC
–2V; T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
OH
V
OL
V
OUT
V
DIFF_OUT
Parameter
Output HIGH Voltage
Output LOW Voltage
Output Voltage Swing
Differential Output Voltage Swing
See Figures 2a.
See Figures 2b.
Condition
Min
Typ
Max
Units
V
V
mV
mV
V
CC
–1.145 V
CC
–1.020 V
CC
–0.895
V
CC
–1.945 V
CC
–1.820 V
CC
–1.695
550
1100
800
1600
1050
2100
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended
periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB.
θ
JA
and
Ψ
JB
values are
determined for a 4-layer board in still-air, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
3
M9999-080505
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
Precision Edge
®
SY89834U
AC ELECTRICAL CHARACTERISTICS
(5)
V
CC
= 2.5V
±5%
or V
CC
= 3.3V
±10%
, R
L
= 50Ω to V
CC
–2V; T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
f
MAX
t
pd
t
SW
t
SKEW
t
JITTER
Parameter
Maximum Frequency
Propagation Delay
Switchover Time
Within-Device Skew
Part-to-Part Skew
Data
Random Jitter (RJ)
Deterministic Jitter (DJ)
Clock
Cycle-to-Cycle Jitter
Total Jitter (TJ)
DC
t
S
t
H
t
r
, t
f
Notes:
5.
6.
7.
8.
9.
High-frequency AC parameters are guaranteed by design and characterization.
V
IH
= 2.0V, V
IL
= 0.8V, 50% duty cycle. Delay measured at 100MHz from the crossing of the input signal with V
CC
/2 as the crossing of the
differential output signal. See Figure 1.
Within device skew is measured between two different outputs under identical input transitions.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective
inputs.
Random jitter is measured with a K28.7 pattern, measured at
≤f
MAX
.
Condition
Input t
r
/ t
f
≥
350ps
IN-to-Q
SEL-to-Q
Note 7
Note 8
Note 9
Note 10
Note 11
Note 12
Input t
r
/t
f
≥
350ps, Note 13
EN to IN1, IN
EN to IN1, IN
Note 14 and Note 15
Note 14 and Note 15
Note 6
Min
1.0
200
200
Typ
Max
Units
GHz
320
320
5
500
500
20
300
1
10
1
10
ps
ps
ps
ps
ps
RMS
ps
PP
ps
RMS
ps
PP
%
ps
ps
Duty Cycle
Set-Up Time
Hold Time
45
300
500
70
50
55
Output Rise/Fall Times
(20% to 80%)
140
225
ps
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23
–1 PRBS pattern.
11. Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs.
T
JITTER_CC
= T
n
– T
n+1
, where T is the time between rising edges of the output signal.
12. Total jitter definition: with an ideal clock input frequency of
≤
f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by more
than the specified peak-to-peak jitter value.
13. If t
r
/t
f
is less than 350ps, the duty cycle distortion will increase beyond the duty cycle limits.
14. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications
set-up and hold times do not apply.
15. See “Timing Diagrams,” Figure 1a.
4
M9999-080505
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
Precision Edge
®
SY89834U
TIMING DIAGRAMS
EN
V
CC
/2
t
S
V
IN
IN
V
CC
/2
t
pd
V
CC
/2
V
CC
/2
V
CC
/2
t
pd
V
OUT
t
H
V
CC
/2
/Q
Q
Figure 1a. Timing Diagram
(EN, IN1, IN2)
IN2
IN1
HIGH
LOW
SEL
V
CC
/2
/Q
Q
t
SWITCHOVER
V
CC
/2
t
SWITCHOVER
V
OUT
Figure 1b. Timing Diagram
(SEL)
SINGLE-ENDED AND DIFFERENTIAL SWINGS
V
OUT
V
DIFF_OUT
Figure 2a. Single-Ended Swing
Figure 2b. Differential Swing
5
M9999-080505
hbwhelp@micrel.com or (408) 955-1690
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