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ATF1504AS-10AU44

CategoryProgrammable logic devices    Programmable logic   
File Size371KB,33 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
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ATF1504AS-10AU44 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMicrochip
package instructionTQFP, TQFP44,.47SQ,32
Reach Compliance Codecompliant
Factory Lead Time12 weeks
Samacsys Confidence3
Samacsys StatusReleased
Samacsys PartID468584
Samacsys Pin Count44
Samacsys Part CategoryIntegrated Circuit
Samacsys Package CategoryQuad Flat Packages
Samacsys Footprint Name44A - 44-lead, 10 x 10mm
Samacsys Released Date2020-05-28 05:40:14
Is SamacsysN
Other featuresPOWER -UP RESET; SECURITY FUSE
maximum clock frequency125 MHz
In-system programmableYES
JESD-30 codeS-PQFP-G44
JESD-609 codee3
JTAG BSTYES
length10 mm
Humidity sensitivity level3
Dedicated input times
Number of I/O lines32
Number of entries32
Number of macro cells64
Output times32
Number of product terms40
Number of terminals44
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize0 DEDICATED INPUTS, 32 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeTQFP
Encapsulate equivalent codeTQFP44,.47SQ,32
Package shapeSQUARE
Package formFLATPACK, THIN PROFILE
Peak Reflow Temperature (Celsius)260
Programmable logic typeEE PLD
propagation delay10 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width10 mm
Base Number Matches1
Features
High-density, High-performance, Electrically-erasable Complex Programmable
Logic Device
– 64 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44, 68, 84, 100 Pins
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation up to 125 MHz
– Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
Advanced Power Management Features
– Automatic µA Standby for “L” Version
– Pin-controlled 1 mA Standby Mode
– Programmable Pin-keeper Circuits on Inputs and I/Os
– Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
3.3V or 5.0V I/O Pins
Security Fuse Feature
High-
performance
Complex
Programmable
Logic Device
ATF1504AS
ATF1504ASL
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent – Latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
V
CC
Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Rev. 0950N–PLD–07/02
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