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74AHC02PW

Description
Logic Type: NOR Gate Additional Features:-
Categorylogic    logic   
File Size78KB,14 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
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74AHC02PW Overview

Logic Type: NOR Gate Additional Features:-

74AHC02PW Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNexperia
package instruction4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14
Reach Compliance Codecompliant
ECCN codeEAR99
Is SamacsysN
seriesAHC/VHC/H/U/V
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length5 mm
Logic integrated circuit typeNOR GATE
Humidity sensitivity level1
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)14.5 ns
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width4.4 mm
Base Number Matches1
74AHC02; 74AHCT02
Quad 2-input NOR gate
Rev. 04 — 21 May 2008
Product data sheet
1. General description
The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.
2. Features
I
I
I
I
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accept voltages higher than V
CC
Input levels:
N
For 74AHC02: CMOS level
N
For 74AHCT02: TTL level
I
ESD protection:
N
HBM EIA/JESD22-A114E exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V
N
CDM EIA/JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC02
74AHC02D
74AHC02PW
74AHC02BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SO14
TSSOP14
DHVQFN14
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT108-1
SOT402-1
Description
Version
Type number
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm

74AHC02PW Related Products

74AHC02PW
Description Logic Type: NOR Gate Additional Features:-
Is it Rohs certified? conform to
Maker Nexperia
package instruction 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14
Reach Compliance Code compliant
ECCN code EAR99
Is Samacsys N
series AHC/VHC/H/U/V
JESD-30 code R-PDSO-G14
JESD-609 code e4
length 5 mm
Logic integrated circuit type NOR GATE
Humidity sensitivity level 1
Number of functions 4
Number of entries 2
Number of terminals 14
Maximum operating temperature 125 °C
Minimum operating temperature -40 °C
Package body material PLASTIC/EPOXY
encapsulated code TSSOP
Package shape RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260
propagation delay (tpd) 14.5 ns
Certification status Not Qualified
Maximum seat height 1.1 mm
Maximum supply voltage (Vsup) 5.5 V
Minimum supply voltage (Vsup) 2 V
Nominal supply voltage (Vsup) 5 V
surface mount YES
technology CMOS
Temperature level AUTOMOTIVE
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form GULL WING
Terminal pitch 0.65 mm
Terminal location DUAL
Maximum time at peak reflow temperature 30
width 4.4 mm
Base Number Matches 1
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