74LVC1G74
Single D-type flip-flop with set and reset;
positive edge trigger
Rev. 14 — 27 December 2018
Product data sheet
1. General description
The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs,
clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry
disables the output, preventing damaging backflow current through the device when it is powered
down.
The set and reset are asynchronous active LOW inputs and operate independently of the clock
input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition
of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock
transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall
times.
2. Features and benefits
•
•
•
•
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
•
JESD8-7 (1.65 V to 1.95 V)
•
JESD8-5 (2.3 V to 2.7 V)
•
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
±24 mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
•
•
•
•
•
•
•
•
Nexperia
74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LVC1G74DP
74LVC1G74DC
74LVC1G74GT
74LVC1G74GF
74LVC1G74GM
74LVC1G74GN
74LVC1G74GS
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
Name
TSSOP8
VSSOP8
XSON8
XSON8
XQFN8
XSON8
XSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
plastic extremely thin small outline package;
no leads; 8 terminals; body 1 × 1.95 × 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1 × 0.5 mm
plastic, extremely thin quad flat package;
no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2 × 1.0 × 0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1.0 × 0.35 mm
Version
SOT505-2
SOT765-1
SOT833-1
SOT1089
SOT902-2
SOT1116
SOT1203
4. Marking
Table 2. Marking codes
Type number
74LVC1G74DP
74LVC1G74DC
74LVC1G74GT
74LVC1G74GF
74LVC1G74GM
74LVC1G74GN
74LVC1G74GS
[1]
Marking code
[1]
V74
V74
V74
Y4
V74
Y4
Y4
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
SD
D
CP
SD
D
CP
FF
Q
RD
RD
001aah757
Q
Q
S
Q
C1
1D
R
001aah758
Fig. 1.
Logic symbol
Fig. 2.
IEC logic symbol
74LVC1G74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 14 — 27 December 2018
2 / 21
Nexperia
74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
C
Q
C
C
C
D
C
RD
SD
CP
C
C
C
C
Q
C
mna421
Fig. 3.
Logic diagram
6. Pinning information
6.1. Pinning
74LVC1G74
CP
1
8
V
CC
74LVC1G74
CP
D
Q
GND
1
2
3
4
001aab659
D
2
7
SD
8
7
6
5
V
CC
SD
RD
Q
Q
3
6
RD
GND
4
5
Q
001aab658
Transparent top view
Fig. 4.
Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
terminal 1
index area
SD
1
Fig. 5.
74LVC1G74
V
CC
Pin configuration SOT833-1, SOT1089, SOT1116
and SOT1203 (XSON8)
8
7
CP
RD
2
6
D
GND
4
Q
3
5
Q
001aaf641
Transparent top view
Fig. 6.
Pin configuration SOT902-2 (XQFN8)
74LVC1G74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 14 — 27 December 2018
3 / 21
Nexperia
74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
6.2. Pin description
Table 3. Pin description
Symbol
Pin
SOT505-2, SOT765-1, SOT833-1,
SOT1089, SOT1116 and SOT1203
CP
D
Q
GND
Q
RD
SD
V
CC
1
2
3
4
5
6
7
8
SOT902-2
7
6
5
4
3
2
1
8
clock input (LOW-to-HIGH, edge-triggered)
data input
complement output
ground (0 V)
true output
asynchronous reset-direct input (active LOW)
asynchronous set-direct input (active LOW)
supply voltage
Description
7. Functional description
Table 4. Function table for asynchronous operation
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Input
SD
L
H
L
RD
H
L
L
CP
X
X
X
D
X
X
X
Output
Q
H
L
H
Q
L
H
H
Table 5. Function table for synchronous operation
H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition;
Q
n+1
= state after the next LOW-to-HIGH CP transition.
Input
SD
H
H
RD
H
H
CP
↑
↑
D
L
H
Output
Q
n+1
L
H
Q
n+1
H
L
74LVC1G74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 14 — 27 December 2018
4 / 21
Nexperia
74LVC1G74
Single D-type flip-flop with set and reset; positive edge trigger
8. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
Conditions
V
I
< 0 V
[1]
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode; V
CC
= 0 V
V
O
= 0 V to V
CC
[1]
[1]
Min
-0.5
-50
-0.5
-
-0.5
-0.5
-
-
-100
Max
+6.5
-
+6.5
±50
+6.5
±50
100
-
300
+150
Unit
V
mA
V
mA
V
mA
mA
mA
mW
°C
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
T
amb
= -40 °C to +125 °C
[2]
V
CC
+ 0.5 V
-
-65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP8 packages: above 55 °C the value of P
tot
derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110 °C the value of P
tot
derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 °C the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 7. Operating conditions
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
1.65
0
0
0
-40
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
74LVC1G74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 14 — 27 December 2018
5 / 21
京公网安备 11010802033920号
EEWORLD
