HEF4040B
12-stage binary ripple counter
Rev. 9 — 23 March 2016
Product data sheet
1. General description
The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The
counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter
stages and forces all outputs LOW, independent of CP. Each counter stage is a static
toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to its
Schmitt trigger action.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall time
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C
to +85
C
Complies with JEDEC standard JESD 13-B
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters
4. Ordering information
Table 1.
Ordering information
All types operate from
40
C to +85
C.
Type number
HEF4040BT
Package
Name
SO16
Description
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT109-1
Nexperia
HEF4040B
12-stage binary ripple counter
5. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic diagram
Fig 3.
Timing diagram
HEF4040B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 9 — 23 March 2016
2 of 13
Nexperia
HEF4040B
12-stage binary ripple counter
6. Pinning information
6.1 Pinning
Fig 4.
Pin configuration
6.2 Pin description
Table 2.
Symbol
V
SS
Q0 to Q11
CP
MR
V
DD
Pin description
Pin
8
9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1
10
11
16
Description
ground supply voltage
parallel output
clock input (HIGH-to-LOW edge-triggered)
master reset input (active HIGH)
supply voltage
HEF4040B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 9 — 23 March 2016
3 of 13
Nexperia
HEF4040B
12-stage binary ripple counter
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
I
IK
V
I
I
OK
I
I/O
I
DD
T
stg
T
amb
P
tot
P
[1]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
DD
+ 0.5 V
V
O
<
0.5
V or V
O
> V
DD
+ 0.5 V
Min
0.5
-
0.5
-
-
-
65
40
Max
+18
10
V
DD
+ 0.5
10
10
50
+150
+85
500
100
Unit
V
mA
V
mA
mA
mA
C
C
mW
mW
SO16 package
per output
[1]
-
-
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
8. Recommended operating conditions
Table 4.
Symbol
V
DD
V
I
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
ambient temperature
input transition rise and fall rate
in free air
V
DD
= 5 V
V
DD
= 10 V
V
DD
= 15 V
Conditions
Min
3
0
40
-
-
-
Typ
-
-
-
-
-
-
Max
15
V
DD
+85
3.75
0.5
0.08
Unit
V
V
C
ms/V
ms/V
ms/V
9. Static characteristics
Table 5.
Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
; unless otherwise specified.
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
I
O
< 1
A
V
DD
5V
10 V
15 V
V
IL
LOW-level input voltage
I
O
< 1
A
5V
10 V
15 V
V
OH
HIGH-level output voltage
I
O
< 1
A
5V
10 V
15 V
HEF4040B
T
amb
=
40 C
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
Max
-
-
-
1.5
3.0
4.0
-
-
-
T
amb
= 25
C
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
Max
-
-
-
1.5
3.0
4.0
-
-
-
T
amb
= 85
C
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
©
Unit
V
V
V
V
V
V
V
V
V
Max
-
-
-
1.5
3.0
4.0
-
-
-
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 9 — 23 March 2016
4 of 13
Nexperia
HEF4040B
12-stage binary ripple counter
Table 5.
Static characteristics
…continued
V
SS
= 0 V; V
I
= V
SS
or V
DD
; unless otherwise specified.
Symbol Parameter
V
OL
LOW-level output voltage
Conditions
I
O
< 1
A
V
DD
5V
10 V
15 V
I
OH
HIGH-level output current
V
O
= 2.5 V
V
O
= 4.6 V
V
O
= 9.5 V
V
O
= 13.5 V
I
OL
LOW-level output current
V
O
= 0.4 V
V
O
= 0.5 V
V
O
= 1.5 V
I
LI
I
DD
input leakage current
supply current
I
O
= 0 A
5V
5V
10 V
15 V
5V
10 V
15 V
15 V
5V
10 V
15 V
C
I
input capacitance
-
T
amb
=
40 C
Min
-
-
-
-
-
-
-
0.52
1.3
3.6
-
-
-
-
-
Max
0.05
0.05
0.05
1.7
0.52
1.3
3.6
-
-
-
0.3
20
40
80
-
T
amb
= 25
C
Min
-
-
-
-
-
-
-
0.44
1.1
3.0
-
-
-
-
-
Max
0.05
0.05
0.05
1.4
0.44
1.1
3.0
-
-
-
0.3
20
40
80
7.5
T
amb
= 85
C
Min
-
-
-
-
-
-
-
0.36
0.9
2.4
-
-
-
-
-
Max
0.05
0.05
0.05
1.1
0.36
0.9
2.4
-
-
-
1.0
150
300
600
-
V
V
V
mA
mA
mA
mA
mA
mA
mA
A
A
A
A
pF
Unit
10. Dynamic characteristics
Table 6.
Dynamic characteristics
V
SS
= 0 V; T
amb
= 25
C; unless otherwise specified; for test circuit see
Figure 6.
Symbol
t
PHL
Parameter
HIGH to LOW
propagation delay
Conditions
CP
Q0
see
Figure 5
V
DD
5V
10 V
15 V
Qn
Qn + 1
5V
10 V
15 V
MR
Qn
see
Figure 5
5V
10 V
15 V
t
PLH
LOW to HIGH
propagation delay
CP
Q0
see
Figure 5
5V
10 V
15 V
Qn
Qn + 1
5V
10 V
15 V
t
t
transition time
see
Figure 5
5V
10 V
15 V
[2]
[2]
[2]
[3]
[2]
[2]
[2]
Extrapolation formula
[1]
78 ns + (0.55 ns/pF)C
L
34 ns + (0.23 ns/pF)C
L
27 ns + (0.16 ns/pF)C
L
(0.55 ns/pF)C
L
(0.23 ns/pF)C
L
(0.16 ns/pF)C
L
63 ns + (0.55 ns/pF)C
L
29 ns + (0.23 ns/pF)C
L
22 ns + (0.16 ns/pF)C
L
58 ns + (0.55 ns/pF)C
L
29 ns + (0.23 ns/pF)C
L
22 ns + (0.16 ns/pF)C
L
(0.55 ns/pF)C
L
(0.23 ns/pF)C
L
(0.16 ns/pF)C
L
10 ns + (1.00 ns/pF)C
L
9 ns + (0.42 ns/pF)C
L
6 ns + (0.28 ns/pF)C
L
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ
105
45
35
35
15
10
90
40
30
85
40
30
35
15
10
60
30
20
Max
210
90
70
70
30
20
180
80
60
170
80
60
70
30
20
120
60
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HEF4040B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 9 — 23 March 2016
5 of 13
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