74HCT573PW,118 datasheet, PDF - EEWORLD Datasheet

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74HCT573PW,118: DescriptionLatch Transparent 3-ST 8-CH D-Type 20-Pin TSSOP T/R; Categorylatch; File Size729KB，20 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

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74HCT573PW,118 Overview

Latch Transparent 3-ST 8-CH D-Type 20-Pin TSSOP T/R

74HCT573PW,118 Parametric

Parameter Name	Attribute value
EU restricts the use of certain hazardous substances	Compliant
ECCN (US)	EAR99
Part Status	Active
HTS	8542.39.00.01
Type	D-Type
Logic Family	HCT
Latch Mode	Transparent
Number of Channels per Chip	8
Number of Elements per Chip	1
Number of Inputs per Chip	8
Number of Input Enables per Element	1
Number of Selection Inputs per Element	0
Number of Outputs per Chip	8
Number of Output Enables per Element	1
Bus Hold	No
Set/Reset	No
Polarity	Non-Inverting
Maximum Propagation Delay Time @ Maximum CL (ns)	35@4.5V
Absolute Propagation Delay Time (ns)	53
Process Technology	CMOS
Output Type	3-State
Maximum Low Level Output Current (mA)	6
Maximum High Level Output Current (mA)	-6
Minimum Operating Supply Voltage (V)	4.5
Typical Operating Supply Voltage (V)	5
Maximum Operating Supply Voltage (V)	5.5
Maximum Quiescent Current (uA)	8
Propagation Delay Test Condition (pF)	50
Minimum Operating Temperature (°C)	-40
Maximum Operating Temperature (°C)	125
Packaging	Tape and Reel
Supplier Package	TSSOP
Pin Count	20
Mounting	Surface Mount
Package Height	0.95(Max)
Package Length	6.6(Max)
Package Width	4.5(Max)
PCB changed	20

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74HC573; 74HCT573

Octal D-type transparent latch; 3-state

Rev. 7 — 4 March 2016

Product data sheet

1. General description

The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The

device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data

at the inputs enter the latches. In this condition the latches are transparent, a latch output

will change each time its corresponding D-input changes. When LE is LOW the latches

store the information that was present at the inputs a set-up time preceding the

HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a

high-impedance OFF-state. Operation of the OE input does not affect the state of the

latches. Inputs include clamp diodes. This enables the use of current limiting resistors to

interface inputs to voltages in excess of V

2. Features and benefits



Input levels:



For 74HC573: CMOS level



For 74HCT573: TTL level



Inputs and outputs on opposite sides of package allowing easy interface with

microprocessors



Useful as input or output port for microprocessors and microcomputers



3-state non-inverting outputs for bus-oriented applications



Common 3-state output enable input



Multiple package options



Complies with JEDEC standard no. 7 A



ESD protection:



HBM JESD22-A114F exceeds 2 000 V



MM JESD22-A115-A exceeds 200 V



Specified from

40 C

to +85

C

and from

40 C

to +125

C

74HCT573PW,118 Related Products

	74HCT573PW,118	74HC573BQ,115	74HCT573DB,118	74HCT573BQ,115	74HCT573PW,112
Description	Latch Transparent 3-ST 8-CH D-Type 20-Pin TSSOP T/R	Latch Transparent 3-ST 8-CH D-Type 20-Pin DHVQFN EP T/R	Latch Transparent 3-ST 8-CH D-Type 20-Pin SSOP T/R	Latch Transparent 3-ST 8-CH D-Type 20-Pin DHVQFN EP T/R	Latch Transparent 3-ST 8-CH D-Type 20-Pin TSSOP Bulk
EU restricts the use of certain hazardous substances	Compliant	Compliant	Compliant	Compliant	Compliant
ECCN (US)	EAR99	EAR99	EAR99	EAR99	EAR99
Part Status	Active	Active	LTB	Active	LTB
HTS	8542.39.00.01	8542.39.00.01	8542.39.00.01	8542.39.00.01	8542.39.00.01
Type	D-Type	D-Type	D-Type	D-Type	D-Type
Logic Family	HCT	HC	HCT	HCT	HCT
Latch Mode	Transparent	Transparent	Transparent	Transparent	Transparent
Number of Channels per Chip	8	8	8	8	8
Number of Elements per Chip	1	1	1	1	1
Number of Inputs per Chip	8	8	8	8	8
Number of Input Enables per Element	1	1	1	1	1
Number of Outputs per Chip	8	8	8	8	8
Number of Output Enables per Element	1	1	1	1	1
Bus Hold	No	No	No	No	No
Set/Reset	No	No	No	No	No
Polarity	Non-Inverting	Non-Inverting	Non-Inverting	Non-Inverting	Non-Inverting
Maximum Propagation Delay Time @ Maximum CL (ns)	35@4.5V	30@4.5V\|26@6V\|150@2V	35@4.5V	35@4.5V	35@4.5V
Absolute Propagation Delay Time (ns)	53	225	53	53	53
Process Technology	CMOS	CMOS	CMOS	CMOS	CMOS
Output Type	3-State	3-State	3-State	3-State	3-State
Maximum Low Level Output Current (mA)	6	7.8	6	6	6
Maximum High Level Output Current (mA)	-6	-7.8	-6	-6	-6
Minimum Operating Supply Voltage (V)	4.5	2	4.5	4.5	4.5
Typical Operating Supply Voltage (V)	5	5	5	5	5
Maximum Operating Supply Voltage (V)	5.5	6	5.5	5.5	5.5
Maximum Quiescent Current (uA)	8	8	8	8	8
Propagation Delay Test Condition (pF)	50	50	50	50	50
Minimum Operating Temperature (°C)	-40	-40	-40	-40	-40
Maximum Operating Temperature (°C)	125	125	125	125	125
Packaging	Tape and Reel	Tape and Reel	Tape and Reel	Tape and Reel	Bulk
Supplier Package	TSSOP	DHVQFN EP	SSOP	DHVQFN EP	TSSOP
Pin Count	20	20	20	20	20
Mounting	Surface Mount	Surface Mount	Surface Mount	Surface Mount	Surface Mount
Package Height	0.95(Max)	0.88	1.8(Max)	0.88	0.95(Max)
Package Length	6.6(Max)	4.5	7.4(Max)	4.5	6.6(Max)
Package Width	4.5(Max)	2.5	5.4(Max)	2.5	4.5(Max)
PCB changed	20	20	20	20	20

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