Total Power Dissipation on FR−4 Board (Note 1) @ T
A
= 25°C
Junction and Storage Temperature Range
Lead Solder Temperature
−
Maximum (10 Second Duration)
°P
D
°
T
J
, T
stg
T
L
Symbol
Value
±30
±30
40
16
400
500
−55
to +150
260
Unit
kV
A
kV
V
mW
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. FR−4 printed circuit board, single−sided copper, mounting pad 1 cm
2
.
See Application Note AND8308/D for further description of survivability specs.
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
I
PP
V
C
V
RWM
I
R
V
BR
I
T
I
F
V
F
P
pk
C
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
PP
Working Peak Reverse Voltage
Maximum Reverse Leakage Current @ V
RWM
Breakdown Voltage @ I
T
Test Current
Forward Current
Forward Voltage @ I
F
Peak Power Dissipation
Max. Capacitance @V
R
= 0 and f = 1 MHz
I
PP
V
C
V
BR
V
RWM
I
R
V
F
I
T
V
I
F
I
Uni−Directional
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
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2
ESD5Z2.5T1G Series, SZESD5Z2.5T1G Series
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted, V
F
= 1.1 V Max. @ I
F
= 10 mA for all types)
V
RWM
(V)
Device
Marking
ZD
ZE
ZF
ZG
ZH
ZM
I
R
(mA)
@ V
RWM
V
BR
(V)
@ I
T
(Note 2)
V
C
(V)
@ I
PP
=
5.0 A
†
V
C
(V) @
Max I
PP
†
I
PP
(A)
†
P
pk
(W)
†
C
(pF)
I
T
V
C
Per
IEC61000−4−2
(Note 3)
Figures 1 and 2
See Below
(Note 4)
Device*
ESD5Z2.5T1G/T5G
ESD5Z3.3T1G/T5G
ESD5Z5.0T1G/T5G
ESD5Z6.0T1G/T5G
ESD5Z7.0T1G/T5G
ESD5Z12T1G/T5G
Max
2.5
3.3
5.0
6.0
7.0
12
Max
6.0
0.05
0.05
0.01
0.01
0.01
Min
4.0
5.0
6.2
6.8
7.5
14.1
mA
1.0
1.0
1.0
1.0
1.0
1.0
Typ
6.5
8.4
11.6
12.4
13.5
17
Max
10.9
14.1
18.6
20.5
22.7
25
Max
11.0
11.2
9.4
8.8
8.8
9.6
Max
120
158
174
181
200
240
Typ
145
105
80
70
65
55
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
* Includes SZ-prefix devices where applicable.
†Surge current waveform per Figure 5.
2. V
BR
is measured with a pulse test current I
T
at an ambient temperature of 25°C.
3. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
4. ESD5Z5.0T1G shown below. Other voltages available upon request.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV contact per IEC 61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV contact per IEC 61000−4−2
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3
ESD5Z2.5T1G Series, SZESD5Z2.5T1G Series
IEC 61000−4−2 Spec.
Test Volt-
age (kV)
2
4
6
8
First Peak
Current
(A)
7.5
15
22.5
30
Current at
30 ns (A)
4
8
12
16
Current at
60 ns (A)
2
4
6
8
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
I @ 30 ns
IEC61000−4−2 Waveform
I
peak
100%
90%
Level
1
2
3
4
Figure 3. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
50
W
Cable
50
W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D
−
Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
% OF PEAK PULSE CURRENT
90
80
70
60
50
40
30
20
10
0
0
20
t
P
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
t
r
PEAK VALUE I
RSM
@ 8
ms
PULSE WIDTH (t
P
) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8
ms
HALF VALUE I
RSM
/2 @ 20
ms
40
t, TIME (ms)
60
80
Figure 5. 8 X 20
ms
Pulse Waveform
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4
ESD5Z2.5T1G Series, SZESD5Z2.5T1G Series
PACKAGE DIMENSIONS
SOD−523
CASE 502
ISSUE E
−X−
D
−Y−
E
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO-
TRUSIONS, OR GATE BURRS.
DIM
A
b
c
D
E
H
E
L
L2
MILLIMETERS
MIN
NOM
MAX
0.50
0.60
0.70
0.25
0.30
0.35
0.07
0.14
0.20
1.10
1.20
1.30
0.70
0.80
0.90
1.50
1.60
1.70
0.30 REF
0.15
0.20
0.25
b
0.08
1
M
2
X Y
TOP VIEW
A
c
H
E
SIDE VIEW
2X
STYLE 1:
PIN 1. CATHODE (POLARITY BAND)
2. ANODE
L
2X
RECOMMENDED
SOLDERING FOOTPRINT*
1.80
0.40
2X
0.48
2X
L2
BOTTOM VIEW
PACKAGE
OUTLINE
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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