MC74HC4060A
14-Stage Binary Ripple
Counter With Oscillator
High−Performance Silicon−Gate CMOS
The MC74HC4060A is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 14 master−slave flip−flops and an oscillator
with a frequency that is controlled either by a crystal or by an RC
circuit connected externally. The output of each flip−flop feeds the
next and the frequency at each output is half of that of the preceding
one. The state of the counter advances on the negative−going edge of
the Osc In. The active−high Reset is asynchronous and disables the
oscillator to allow very low power consumption during stand−by
operation.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with Osc Out 2 of the
HC4060A.
Features
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SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
V
CC
16
Q10
15
Q8
14
Q9
13
Osc Osc
Reset Osc In Out 1 Out 2
12
11
10
9
•
•
•
•
•
•
•
•
1
Q12
2
Q13
3
Q14
4
Q6
5
Q5
6
Q7
7
Q4
8
GND
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With JEDEC Standard No. 7A Requirements
Chip Complexity: 390 FETs or 97.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
LOGIC DIAGRAM
Osc Out 1 Osc Out 2
10
9
7
5
4
6
14
13
15
1
2
3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q12
Q13
Q14
16−Lead Package
(Top View)
MARKING DIAGRAMS
16
HC4060AG
AWLYWW
1
SOIC−16
A
L, WL
Y, YY
W, WW
G or
G
1
TSSOP−16
16
HC40
60A
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Clock
Reset
L
L
H
Output State
No Change
Advance to Next State
All Outputs Are Low
Osc In
11
X
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Reset
12
Pin 16 = V
CC
Pin 8 = GND
©
Semiconductor Components Industries, LLC, 2016
1
June, 2016 − Rev. 10
Publication Order Number:
MC74HC4060A/D
MC74HC4060A
MAXIMUM RATINGS
Symbol
V
CC
V
in
V
out
I
in
I
out
I
CC
P
D
T
stg
T
L
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
SOIC Package†
TSSOP Package†
Value
–0.5 to +7.0
–0.5 to V
CC
+ 0.5
–0.5 to V
CC
+ 0.5
±20
±25
±50
500
450
– 65 to + 150
260
Unit
V
V
V
mA
mA
mA
mW
_C
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature Range, All Package Types
Input Rise/Fall Time
(Figure 1)
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Min
2.5*
0
–55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
*The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested at
2.0 V by driving Pin 11 with an external clock source.
DC CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage
Condition
V
out
= 0.1V or V
CC
−0.1V
|I
out
|
≤
20mA
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
2.4mA
|I
out
|
≤
4.0mA
|I
out
|
≤
5.2mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
2.4mA
|I
out
|
≤
4.0mA
|I
out
|
≤
5.2mA
3.0
4.5
6.0
Guaranteed Limit
−55 to 25°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
≤85°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
≤125°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.20
3.70
5.20
0.1
0.1
0.1
0.40
0.40
0.40
V
Unit
V
V
IL
Maximum Low−Level Input Voltage
V
out
= 0.1V or V
CC
− 0.1V
|I
out
|
≤
20mA
V
V
OH
Minimum High−Level Output Voltage
(Q4−Q10, Q12−Q14)
V
in
= V
IH
or V
IL
|I
out
|
≤
20mA
V
in
=V
IH
or V
IL
V
V
OL
Maximum Low−Level Output Voltage
(Q4−Q10, Q12−Q14)
V
in
= V
IH
or V
IL
|I
out
|
≤
20mA
V
in
= V
IH
or V
IL
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2
MC74HC4060A
DC CHARACTERISTICS
(Voltages Referenced to GND) (continued)
Symbol
V
OH
Parameter
Minimum High−Level Output Voltage
(Osc Out 1, Osc Out 2)
Condition
V
in
= V
CC
or GND
|I
out
|
≤
20mA
V
in
=V
CC
or GND
|I
out
|
≤
0.7mA
|I
out
|
≤
1.0mA
|I
out
|
≤
1.3mA
V
CC
V
2.0
4.5
6.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
0.7mA
|I
out
|
≤
1.0mA
|I
out
|
≤
1.3mA
3.0
4.5
6.0
6.0
6.0
Guaranteed Limit
−55 to 25°C
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
4
≤85°C
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
40
≤125°C
1.9
4.4
5.9
2.20
3.70
5.20
0.1
0.1
0.1
0.40
0.40
0.40
±1.0
160
mA
mA
V
Unit
V
V
OL
Maximum Low−Level Output Voltage
(Osc Out 1, Osc Out 2)
V
in
= V
CC
or GND
|I
out
|
≤
20mA
V
in
=V
CC
or GND
I
in
I
CC
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0mA
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
−55 to 25°C
6.0
10
30
50
300
180
60
51
500
350
250
200
195
75
39
33
75
60
15
13
≤85°C
9.0
14
28
45
375
200
75
64
750
450
275
220
245
100
49
42
95
75
19
16
≤125°C
8.0
12
25
40
450
250
90
75
1000
600
300
250
300
125
61
53
125
95
24
20
Unit
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Osc In to Q4*
(Figures 1 and 4)
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Osc In to Q14*
(Figures 1 and 4)
ns
t
PHL
Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Qn to Qn+1
(Figures 3 and 4)
ns
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
− continued
Symbol
t
TLH
,
t
THL
Parameter
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
V
CC
V
2.0
3.0
4.5
6.0
Guaranteed Limit
−55 to 25°C
75
27
15
13
10
≤85°C
95
32
19
16
10
≤125°C
110
36
22
19
10
Unit
ns
C
in
Maximum Input Capacitance
pF
* For T
A
= 25°C and C
L
= 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
V
CC
= 2.0 V: t
P
= [93.7 + 59.3 (n−1)] ns
V
CC
= 4.5 V: t
P
= [30.25 + 14.6 (n−1)] ns
V
CC
= 3.0 V: t
P
= [61.5+ 34.4 (n−1)] ns
V
CC
= 6.0 V: t
P
= [24.4 + 12 (n−1)] ns
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
2
f
35
+ I
CC
V
CC
.
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
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3
MC74HC4060A
TIMING REQUIREMENTS
(Input t
r
= t
f
= 6 ns)
Symbol
t
rec
Parameter
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
−55 to 25°C
100
75
20
17
75
27
15
13
75
27
15
13
1000
800
500
400
≤85°C
125
100
25
21
95
32
19
16
95
32
19
16
1000
800
500
400
≤125°C
150
120
30
25
110
36
23
19
110
36
23
19
1000
800
500
400
Unit
ns
t
w
Minimum Pulse Width, Clock
(Figure 1)
ns
t
w
Minimum Pulse Width, Reset
(Figure 2)
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
ns
ORDERING INFORMATION
Device
MC74HC4060ADG
MC74HC4060ADR2G
NLV74HC4060ADR2G*
MC74HC4060ADTG
MC74HC4060ADTR2G
NLVHC4060ADTR2G*
Package
SOIC−16
(Pb−Free)
SOIC−16
(Pb−Free)
SOIC−16
(Pb−Free)
TSSOP−16
(Pb−Free)
TSSOP−16
(Pb−Free)
TSSOP−16
(Pb−Free)
Shipping
†
48 Units / Rail
2500 Units / Reel
2500 Units / Reel
96 Units / Rail
2500 Units / Reel
2500 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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4
MC74HC4060A
PIN DESCRIPTIONS
INPUTS
Osc In (Pin 11)
Osc Out 1, Osc Out 2 (Pins 9, 10)
Negative−edge triggering clock input. A high−to−low
transition on this input advances the state of the counter. Osc
In may be driven by an external clock source.
Reset (Pin 12)
Active−high reset. A high level applied to this input
asynchronously resets the counter to its zero state (forcing
all Q outputs low) and disables the oscillator.
OUTPUTS
Q4—Q10, Q12−Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)
Oscillator outputs. These pins are used in conjunction
with Osc In and the external components to form an
oscillator. When Osc In is being driven with an external
clock source, Osc Out 1 and Osc Out 2 must be left open
circuited. With the crystal oscillator configuration in
Figure 6, Osc Out 2 must be left open circuited.
Active−high outputs. Each Qn output divides the Clock
input frequency by 2
N
. The user should note the Q1, Q2, Q3
and Q11 are not available as outputs.
SWITCHING WAVEFORMS
t
w
V
CC
GND
1/f
MAX
t
PLH
Q
90%
50%
10%
t
TLH
t
THL
t
PHL
Q
Reset
t
PHL
50%
t
rec
Osc In
50%
GND
50%
GND
t
w
t
f
Osc In
90%
50%
10%
t
r
V
CC
V
CC
Figure 1.
Figure 2.
TEST
POINT
V
CC
Qn
50%
GND
t
PLH
Qn+1
50%
t
PHL
DEVICE
UNDER
TEST
OUTPUT
C
L
*
*Includes all probe and jig capacitance
Figure 3.
Figure 4. Test Circuit
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