NB3RL02
Low Phase-Noise
Two-Channel Clock Fanout
Buffer
The NB3RL02 is a low−skew, low jitter 1:2 clock fan−out buffer,
ideal for use in portable end−equipment, such as mobile phones. With
integrated LDO and output control circuitry.
The MCLK_IN pin has an AC coupling capacitor and will directly
accept a square or sine wave clock input, such as a temperature
compensated crystal oscillator (TCXO). The minimum acceptable
input amplitude of the sine wave is 300 mV peak−to−peak.
The two clock outputs are enabled by control inputs CLK_REQ1
and CLK_REQ2.
The NB3RL02 has an integrated Low−Drop−Out (LDO) voltage
regulator which accepts input voltages from 2.3 V to 5.5 V and outputs
1.8 V at I
out
= 50 mA. This 1.8 V supply is externally available to
provide regulated power to peripheral devices, such as a TCXO.
The adaptive clock output buffers offer controlled slew−rate over a
wide capacitive loading range which minimizes EMI emissions,
maintains signal integrity, and minimizes ringing caused by signal
reflections on the clock distribution lines.
The NB3RL02 is offered in a 0.4 mm pitch wafer−level−chip−scale
(WLCS) package and is optimized for very low standby current
consumption.
Features
♦
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MARKING
DIAGRAMS
WLCSP8
CASE 499BQ
RLYYWW
G
RL
YY
WW
G
= Specific Device Code
= Year
= Work Week
= Pb−Free Package
LOGIC DIAGRAM
•
Low Additive Noise:
•
•
•
•
•
•
−149
dBc/Hz at 10 kHz Offset Phase Noise
♦
0.37 ps (rms) Output Jitter
Limited Output Slew Rate for EMI Reduction
(1 ns to 5 ns/Rise/Fall Time for 10−50 pF Loads)
Regulated 1.8 V Output Supply Available for External Clock Source,
ie. TCX0
Operation to 80 MHz
Ultra−Small Package:
♦
8−ball: 0.4 mm Pitch WLCS
ESD Performance Exceeds JESD 22
♦
2000 V Human−Body Model (A114−A)
♦
200 V Machine Model (A115−A)
♦
1000 V Charged−Device Model (JESD22−C101−A Level III)
These are Pb−Free Devices
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Applications
•
Cellular Phones
•
Global Positioning Systems (GPS)
©
Semiconductor Components Industries, LLC, 2015
August, 2019
−
Rev. 6
1
Publication Order Number:
NB3RL02/D
NB3RL02
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
V
BATT
Parameter
V
BATT
Voltage Range (Note 1)
Voltage range (Note 2)
CLK_REQ_1/2, MCLK_IN
V
LDO
, CLK_OUT_1/2
(Note 1)
I
IK
I
O
Input clamp current at V
BATT
, CLK_REQ_1/2,
and MCLK_IN
Continuous output current
Continuous current through GND, V
BATT
, V
L-
DO
Condition
Min
−0.3
−0.3
−0.3
Max
7
V
BATT
+ 0.3
V
BATT
+ 0.3
−50
$20
$50
2000
1000
200
Unit
V
V
V
I
< 0
CLK_OUT1/2
Continuous current through
GND, V
BATT
, V
LDO
Human−Body Model
Charged−Device Model
Machine Model
mA
mA
mA
V
ESD Rating
T
J
T
A
T
stg
Operating virtual junction temperature
Operating ambient temperature range
Storage temperature range
−40
−40
−55
150
85
150
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functional-
ity should not be assumed, damage may occur and reliability may be affected.
1. The input negative−voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. All voltage values are with respect to network ground terminal.
Table 4. RECOMMENDED OPERATING CONDITIONS
(Note 3)
Symbol
V
BATT
V
I
V
O
V
IH
V
IL
I
OH
I
OL
Input voltage
Input voltage Amplitude
Output voltage
High−level input voltage
Low−level input voltage
High−level output current, DC current
Low−level output current, DC current
Parameter
V
BATT
MCLK_IN, CLK_REQ1/2
CLK_OUT1/2
CLK_REQ1/2
CLK_REQ1/2
Min
2.3
0
0
1.3
0
−8
8
Max
5.5
1.89
1.8
1.89
0.5
Unit
V
V
V
V
V
mA
mA
3. All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation.
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NB3RL02
Table 5. ELECTRICAL CHARACTERISTICS
(
T
A
=
−40°C
to +85°C
)
Symbol
LDO
V
OUT
C
LDO
I
OUT(SC)
I
OUT(PK)
PSR
LDO output voltage
External load capacitance
Short circuit output current
Peak output current
Power supply rejection
R
L
= 0
W
V
BATT
= 2.3 V, V
LDO
= V
OUT
−
5%
V
BATT
= 2.3V,
I
OUT
= 2 mA
f
IN
= 217 Hz
and 1 kHz
f
IN
= 3.25 MHz
t
su
LDO start−up time
V
BATT
= 2.3 V , C
LDO
= 1
mF,
CLK_REQ_n
to V
LDO
= 1.71 V
V
BATT
= 5.5 V , C
LDO
= 10
mF,
CLK_REQ_n
to V
LDO
= 1.71 V
POWER CONSUMPTION
I
SB
I
CCS
I
OB
C
PD
Standby current
Static current consumption
Output buffer average
current
Output power dissipation
capacitance
Device in standby (all VCLK_REQ_n = 0 V)
Device active but not switching,
V
CLK_REQn
= H
f
IN
= 26 MHz, C
LOAD
= 50 pF
f
IN
= 52 MHz, C
LOAD
= 50 pF
f
IN
= 26 MHz
0.2
0.4
4.2
6.0
44
1
1
mA
mA
mA
pF
60
40
0.2
1
ms
ms
I
OUT
= 50 mA
1.71
1
100
55
100
1.8
1.89
10
V
mF
mA
mA
dB
Parameter
Test Conditions
Min
Typ
Max
Unit
MCLK_IN INPUT
I
I
C
I
R
I
f
IN
MCLK_IN, CLK_REQ_1/2
leakage current
MCLK_IN capacitance
MCLK_IN impedance
MCLK_IN frequency range
V
I
= V
LDO
or GND
f
IN
= 26 MHz
f
IN
= 26 MHz
9
3.75
5
26/52
80
1
mA
pF
kW
MHz
MCLK_IN LVCMOS SOURCE
Phase noise
f
IN
= 26 MHz/52 MHz,
tr/tf
v
1 ns
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
Additive jitter
f
IN
= 26 MHz, V
PP
= 0.8 V,
f
IN
= 52 MHz, V
PP
= 0.8 V,
BW = 10 kHz
−
5 MHz
−140/−133
−149/−144
−153/−146
−151/−151
0.37
0.24
10
f
IN
= 26 MHz, DC
IN
= 50%
f
IN
= 52 MHz, DC
IN
= 50%
45
45
50
50
55
55
ps
(rms)
ns
%
dBc/Hz
t
DL
DC
L
MCLK_IN to CLK_OUT_n
propagation delay
Output duty cycle
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm.
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