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MC100LVEP111FAG

Categorylogic    logic   
File Size174KB,14 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
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MC100LVEP111FAG Parametric

Parameter NameAttribute value
Brand NameON Semiconductor
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerON Semiconductor
Parts packaging codeQFP
package instructionLQFP, QFP32,.35SQ,32
Contacts32
Manufacturer packaging code873A-02
Reach Compliance Codecompliant
ECCN codeEAR99
Factory Lead Time1 week
Other featuresNECL MODE OPERATING RANGE: VCC = 0V WITH VEE = -2.375V TO -3.8V
series100LVE
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeS-PQFP-G32
JESD-609 codee3
length7 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level2
Number of functions1
Number of inverted outputs
Number of terminals32
Actual output times10
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP32,.35SQ,32
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)260
power supply+-2.375/+-3.8 V
Prop。Delay @ Nom-Sup0.59 ns
propagation delay (tpd)0.5 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.025 ns
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.8 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyECL
Temperature levelINDUSTRIAL
Terminal surfaceTin (Sn)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width7 mm
MC100LVEP111
2.5V / 3.3V 2:1:10
Differential ECL/PECL/HSTL
Clock Driver
Description
The MC100LVEP111 is a low skew 2:1:10 differential driver, designed
with clock distribution in mind, accepting two clock sources into an input
multiplexer. The PECL input signals can be either differential or
single−ended (if the V
BB
output is used). HSTL inputs can be used when
the LVEP111 is operating under PECL conditions.
The LVEP111 specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device and
from device to device.
To ensure tightest skew, both sides of differential outputs identically
terminate into 50
W
even if only one output is being used. If an output
pair is unused, both outputs may be left open (unterminated) without
affecting skew.
The MC100LVEP111, as with most other ECL devices, can be
operated from a positive V
CC
supply in PECL mode. This allows the
LVEP111 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. Single−ended CLK input operation is limited to a V
CC
3.0 V in PECL mode, or V
EE
v
−3.0 V in NECL mode when using VBB
(See Figure 11). Full operating range is available when using an external
voltage reference (See Figure 10). Designers can take advantage of the
LVEP111’s performance to distribute low skew clocks across the
backplane or the board.
Features
www.onsemi.com
MARKING
DIAGRAMS*
MC100
LVEP111
AWLYYWWG
LQFP−32
FA SUFFIX
CASE 873A
32
1
1
1
32
QFN32
MN SUFFIX
CASE 488AM
A
WL
YY
WW
G or
G
MC100
LVEP111
AWLYYWW
G
85 ps Typical Device−to−Device Skew
20 ps Typical Output−to−Output Skew
Jitter Less than 1 ps RMS
Additive RMS Phase Jitter: 60 fs @ 156.25 MHz, Typ.
Maximum Frequency > 3 GHz Typical
V
BB
Output
430 ps Typical Propagation Delay
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode Operating Range: V
CC
= 2.375 V to 3.8 V
with V
EE
= 0 V
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −2.375 V to −3.8 V
Open Input Default State
LVDS Input Compatible
Fully Compatible with MC100EP111
These are Pb−Free Devices
©
Semiconductor Components Industries, LLC, 2015
1
August, 2015 − Rev. 23
Publication Order Number:
MC100LVEP111/D
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