16 Mbit (x8) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF1681 / SST39VF1682
Data Sheet
The SST39VF1681 / SST39VF1682 are 2M x8 CMOS Multi-Purpose Flash Plus
(MPF+) manufactured with SST proprietary, high performance CMOS Super-
Flash® technology. The split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with alternate approaches.
The SST39VF1681 / SST39VF1682 write (Program or Erase) with a 2.7-3.6V
power supply. These devices conforms to JEDEC standard pinouts for x8 memo-
ries.
Features
• Organized as 2M x8
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Security-ID Feature
– SST: 128 bits; User: 128 bits
• Fast Read Access Time:
– 70 ns
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Latched Address and Data
• Fast Erase and Byte-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Byte-Program Time: 7 µs (typical)
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 64 KByte)
for SST39VF1682
– Bottom Block-Protection (bottom 64 KByte)
for SST39VF1681
• Automatic Write Timing
– Internal V
PP
Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
• Sector-Erase Capability
– Uniform 4 KByte sectors
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and Command sets
• Block-Erase Capability
– Uniform 64 KByte blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-lead TSOP (12mm x 20mm)
• All devices are RoHS compliant
©2011 Silicon Storage Technology, Inc.
www.microchip.com
DS25040A
05/11
16 Mbit Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF1681 / SST39VF1682
Data Sheet
Product Description
The SST39VF168x devices are 2M x8 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST’s
proprietary, high performance CMOS SuperFlash® technology. The split-gate cell design and thick-oxide
tunneling injector attain better reliability and manufacturability compared with alternate approaches. The
SST39VF168x write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC
standard pinouts for x8 memories.
Featuring high performance Byte-Program, the SST39VF168x devices provide a typical Byte-Program
time of 7 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program
operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protec-
tion schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices
are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater
than 100 years.
The SST39VF168x devices are suited for applications that require convenient and economical updat-
ing of program, configuration, or data memory. For all system applications, they significantly improve
performance and reliability, while lowering power consumption. They inherently use less energy during
Erase and Program than alternative flash technologies. The total energy consumed is a function of the
applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter erase time, the total energy consumed dur-
ing any Erase or Program operation is less than alternative flash technologies. These devices also
improve flexibility while lowering the cost for program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-
gram times increase with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the SST39VF168x are offered in both 48-ball TFBGA
and 48-lead TSOP packages. See Figures 2 and 3 for pin assignments.
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
2
16 Mbit Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF1681 / SST39VF1682
Data Sheet
Block Diagram
X-Decoder
SuperFlash
Memory
Memory Address
Address Buffer Latches
Y-Decoder
CE#
OE#
WE#
WP#
RESET#
I/O Buffers and Data Latches
Control Logic
DQ
7
- DQ
0
1243 B1.0
Figure 1:
SST39VF1681 / SST39VF1682 Block Diagram
Pin Description
TOP VIEW (balls facing down)
6
5
4
3
2
1
A14 A13 A15
A10
A9
A11
NC
A16 A17 NC
A12 DQ7 NC
A20 DQ5 NC
NC DQ2 NC
A6
A2
DQ0 NC
A0 VSS
NC DQ6
VDD DQ4
NC DQ3
NC DQ1
1243 48-tfbga B3K P1.0
WE# RST#
NC WP# A19
A8
A4
A18
A5
A7
A3
A1 CE# OE# VSS
A
B
C
D
E
F
G
H
Figure 2:
Pin Assignments for 48-lead TFBGA
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
3
16 Mbit Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF1681 / SST39VF1682
Data Sheet
A16
A15
A14
A13
A12
A11
A10
A9
A20
NC
WE#
RST#
NC
WP#
NC
A19
A18
A8
A7
A6
A5
A4
A3
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard Pinout
Top View
Die Up
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1243 48-tsop P2.0
A17
NC
VSS
A0
DQ7
NC
DQ6
NC
DQ5
NC
DQ4
VDD
NC
DQ3
NC
DQ2
NC
DQ1
NC
DQ0
OE#
VSS
CE#
A1
Figure 3:
Pin Assignments for 48-lead TSOP
Table 1:
Pin Description
Symbol
A
MS1
-A
0
Pin Name
Address Inputs
Functions
To provide memory addresses.
During Sector-Erase A
MS
-A
12
address lines will select the sector.
During Block-Erase A
MS
-A
16
address lines will select the block.
DQ
7
-DQ
0
Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
Write Protect
Reset
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
Unconnected pins.
T1.1 25040
WP#
RST#
CE#
OE#
WE#
V
DD
V
SS
NC
To protect the top/bottom boot block from Erase/Program operation when
grounded.
To reset and return the device to Read mode.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage: 2.7-3.6V
1. A
MS
= Most significant address
A
MS
= A
20
for SST39VF1681/1682
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
4
16 Mbit Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF1681 / SST39VF1682
Data Sheet
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
The SST39VF168x also have the
Auto Low Power
mode which puts the device in a near standby
mode after data has been accessed with a valid Read operation. This reduces the I
DD
active read cur-
rent from typically 9 mA to typically 3 µA. The Auto Low Power mode reduces the typical I
DD
active
read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode
with any address transition or control signal transition used to initiate another Read cycle, with no
access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with
CE# held steadily low, until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF168x is controlled by CE# and OE#, both have to be low for the system
to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected
and only standby power is consumed. OE# is the output control and is used to gate data from the output
pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle tim-
ing diagram for further details (Figure 4).
Byte-Program Operation
The SST39VF168x are programmed on a byte-by-byte basis. Before programming, the sector where
the byte exists must be fully erased. The Program operation is accomplished in three steps. The first
step is the three-byte load sequence for Software Data Protection. The second step is to load byte
address and byte data. During the Byte-Program operation, the addresses are latched on the falling
edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE#
or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after
the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initi-
ated, will be completed within 10 µs. See Figures 5 and 6 for WE# and CE# controlled Program opera-
tion timing diagrams and Figure 20 for flowcharts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform
additional tasks. Any commands issued during the internal Program operation are ignored. During the
command sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39VF168x offer both Sector-Erase and Block-Erase mode. The sector
architecture is based on uniform sector size of 4 KByte. The Block-Erase mode is based on uniform
block size of 64 KByte. The Sector-Erase operation is initiated by executing a six-byte command
sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-
Erase operation is initiated by executing a six-byte command sequence with Block-Erase command
(30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling
edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth
WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase opera-
tion can be determined using either Data# Polling or Toggle Bit methods. See Figures 10 and 11 for
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
5
京公网安备 11010802033920号
EEWORLD
