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STM32L432KBU6

Description
Operating voltage: 1.71V ~ 3.6V CPU bits: 32-Bit CPU core: ARM® Cortex®-M4 Main frequency (MAX): 80MHz ROM type: FLASH Cortex-M4 MCU 80 MHz with 256 Kbytes Flash, USB
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size2MB,149 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
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STM32L432KBU6 Overview

Operating voltage: 1.71V ~ 3.6V CPU bits: 32-Bit CPU core: ARM® Cortex®-M4 Main frequency (MAX): 80MHz ROM type: FLASH Cortex-M4 MCU 80 MHz with 256 Kbytes Flash, USB

STM32L432KBU6 Parametric

Parameter NameAttribute value
Brand NameSTMicroelectronics
Is it Rohs certified?conform to
package instructionHVQCCN,
Manufacturer packaging codeUFQFPN 32 5x5x0.55
Reach Compliance Codecompliant
Factory Lead Time11 weeks
Has ADCYES
Address bus width
bit size32
maximum clock frequency48 MHz
DMA channelYES
External data bus width
length5 mm
Number of I/O lines26
Number of terminals32
PWM channelYES
encapsulated codeHVQCCN
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
speed80 MHz
Maximum supply voltage3.6 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width5 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER, RISC
Base Number Matches1
STM32L432KB STM3L432KC
Ultra-low-power ARM
®
Cortex
®
-M4 32-bit MCU+FPU, 100DMIPS,
up to 256KB Flash, 64KB SRAM, USB FS, analog, audio
Datasheet
-
production data
Features
Ultra-low-power with FlexPowerControl
– 1.71 V to 3.6 V power supply
– -40 °C to 85/105/125 °C temperature range
– 8 nA Shutdown mode (2 wakeup pins)
– 28 nA Standby mode (2 wakeup pins)
– 280 nA Standby mode with RTC
– 1.0 µA Stop 2 mode, 1.28 µA Stop 2 with
RTC
– 84 µA/MHz run mode
– Batch acquisition mode (BAM)
– 4 µs wakeup from Stop mode
– Brown out reset (BOR) in all modes except
shutdown
– Interconnect matrix
Core: ARM
®
32-bit Cortex
®
-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait-state execution
from Flash memory, frequency up to 80 MHz,
MPU, 100DMIPS/1.25DMIPS/MHz (Dhrystone
2.1), and DSP instructions
Performance Benchmark
– 1.25 DMIPS/MHz (Drystone 2.1)
– 273.55 Coremark
®
(3.42 Coremark/MHz @
80 MHz)
Energy Benchmark
– 176.7 ULPBench
®
score
Clock Sources
– 32 kHz crystal oscillator for RTC (LSE)
– Internal 16 MHz factory-trimmed RC (±1%)
– Internal low-power 32 kHz RC (±5%)
– Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
±0.25 % accuracy)
– Internal 48 MHz with clock recovery
– 2 PLLs for system clock, USB, audio, ADC
RTC with HW calendar, alarms and calibration
Up to 3 capacitive sensing channels
May 2016
This is information on a product in full production.
UFQFPN32 (5x5)
11x timers: 1x 16-bit advanced motor-control,
1x 32-bit and 2x 16-bit general purpose, 2x 16-
bit basic, 2x low-power 16-bit timers (available
in Stop mode), 2x watchdogs, SysTick timer
Up to 26 fast I/Os, most 5 V-tolerant
Memories
– Up to 256 KB single bank Flash,
proprietary code readout protection
– 64 KB of SRAM including 16 KB with
hardware parity check
– Quad SPI memory interface
Rich analog peripherals (independent supply)
– 1× 12-bit ADC 5 Msps, up to 16-bit with
hardware oversampling, 200 µA/Msps
– 2x 12-bit DAC, low-power sample and hold
– 1x operational amplifier with built-in PGA
– 2x ultra-low-power comparators
13x communication interfaces
– USB 2.0 full-speed crystal less solution
with LPM and BCD
– 1x SAI (serial audio interface)
– 2x I2C FM+(1 Mbit/s), SMBus/PMBus
– 3x USARTs (ISO 7816, LIN, IrDA, modem)
– 2x SPIs (3x SPIs with the Quad SPI)
– CAN (2.0B Active)
– SWPMI single wire protocol master I/F
– IRTIM (Infrared interface)
14-channel DMA controller
True random number generator
CRC calculation unit, 96-bit unique ID
Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell™
DocID028798 Rev 2
1/149
www.st.com
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