®
SG2525A
SG3525A
REGULATING PULSE WIDTH MODULATORS
.
.
.
.
.
.
.
.
.
.
8 TO 35 V OPERATION
5.1 V REFERENCE TRIMMED TO
±
1 %
100 Hz TO 500 KHz OSCILLATOR RANGE
SEPARATE OSCILLATOR SYNC TERMINAL
ADJUSTABLE DEADTIME CONTROL
INTERNAL SOFT-START
PULSE-BY-PULSE SHUTDOWN
INPUT UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS
LATCHING PWM TO PREVENT MULTIPLE
PULSES
DUAL SOURCE/SINK OUTPUT DRIVERS
DIP16
16(Narrow)
DESCRIPTION
The SG3525A series of pulse width modulator inte-
grated circuits are designed to offer improved per-
formance and lowered external parts count when
used in designing all types of switching power sup-
plies. The on-chip + 5.1 V reference is trimmed to
±
1 % and the input common-mode range of the error
amplifier includes the reference voltage eliminating
external resistors. A sync input to the oscillator al-
lows multiple units to be slaved or a single unit to be
synchronized to an external system clock. A single
resistor between the C
T
and the discharge terminals
provide a wide range of dead time ad- justment.
These devices also feature built-in soft-start circuitry
with only an external timing capacitor required. A
shutdown terminal controls both the soft-start circu-
ity and the output stages, providing instantaneous
turn off through the PWM latch with pulsed shut-
down, as well as soft-start recycle with longer shut-
down commands. These functions are also control-
led by an undervoltage lockout which keeps the out-
puts off and the soft-start capacitor discharged for
sub-normal input voltages. This lockout circuitry in-
cludes approximately 500 mV of hysteresis for jitter-
free operation. Another feature of these PWM cir-
cuits is a latch following the comparator. Once a
PWM pulses has been terminated for any reason,
the outputs will remain off for the duration of the pe-
riod. The latch is reset with each clock pulse. The
output stages are totem-pole designs capable of
sourcing or sinking in excess of 200 mA. The
SG3525A output stage features NOR logic, giving a
LOW output for an OFF state.
PIN CONNECTIONS AND ORDERING NUMBERS
(top view)
Type
SG2525A
SG3525A
Plastic DIP
SG2525AN
SG3525AN
SO16
SG2525AP
SG3525AP
June 2000
1/12
SG2525A-SG3525A
ABSOLUTE MAXIMUM RATINGS
Symbol
V
i
V
C
I
OSC
I
o
I
R
I
T
Supply Voltage
Collector Supply Voltage
Oscillator Charging Current
Output Current, Source or Sink
Reference Output Current
Current through C
T
Terminal
Logic Inputs
Analog Inputs
Total Power Dissipation at T
amb
= 70
°C
Junction Temperature Range
Storage Temperature Range
Operating Ambient Temperature :
SG2525A
SG3525A
Parameter
Value
40
40
5
500
50
5
– 0.3 to + 5.5
– 0.3 to V
i
1000
– 55 to 150
– 65 to 150
– 25 to 85
0 to 70
Unit
V
V
mA
mA
mA
mA
V
V
mW
°C
°C
°C
°C
P
tot
T
j
T
stg
T
op
THERMAL DATA
Symbol
R
th j-pins
R
th j-amb
R
th j-alumina
Parameter
Thermal Resistance Junction-pins
Thermal Resistance Junction-ambient
Thermal Resistance Junction-alumina (*)
Max
Max
Max
SO16
DIP16
50
80
50
Unit
°C/W
°C/W
°C/W
* Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15
×
20 mm ; 0.65 mm
thickness with infinite heatsink.
BLOCK DIAGRAM
2/12
SG2525A-SG3525A
ELECTRICAL CHARACTERISTICS
(continued)
Symbol
Parameter
Test Conditions
Min.
PWM COMPARATOR
Minimum Duty-cycle
•
•
*
Maximum Duty-cycle
Input Threshold
Input Bias Current
Soft Start Current
Soft Start Low Level
Shutdown Threshold
V
SD
= 0 V, V
SS
= 0 V
V
SD
= 2.5 V
To outputs, V
SS
= 5.1 V
T
j
= 25
°C
V
SD
= 2.5 V T
j
= 25
°C
I
sink
= 20 mA
I
sink
= 100 mA
Output High Level
Under-Voltage Lockout
I
C
t
r
*
t
f
*
I
s
Collector Leakage
Rise Time
Fall Time
Supply Current
I
source
= 20 mA
I
source
= 100 mA
V
comp
and V
ss
= High
V
C
= 35 V
C
L
= 1 nF, T
j
= 25
°C
C
L
= 1 nF, T
j
= 25
°C
V
i
= 35 V
100
50
14
18
17
6
0.6
25
Zero Duty-cycle
Maximum Duty-cycle
SHUTDOWN SECTION
50
0.4
0.8
0.4
0.2
0.2
1
19
18
7
8
200
600
300
20
100
50
14
80
0.7
1
1
0.5
0.4
2
18
17
6
0.6
25
50
0.4
0.8
0.4
0.2
0.2
1
19
18
7
8
200
600
300
20
80
0.7
1
1
0.5
0.4
2
µA
V
V
mA
µs
V
V
V
V
V
µA
ns
ns
mA
45
0.7
49
0.9
3.3
0.05
3.6
1
0
45
0.7
49
0.9
3.3
0.05
3.6
1
0
%
%
V
V
µA
SG2525A
Typ.
Max.
Min.
SG3525A
Typ.
Max.
Unit
Shutdown Input Current V
SD
= 2.5 V
*
Shutdown Delay
Output Low Level
OUTPUT DRIVERS (each output) (V
C
= 20 V)
TOTAL STANDBY CURRENT
* These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production.
•
Tested at f
osc
= 40 KHz (R
T
= 3.6 KΩ, C
T
= 10nF, R
D
= 0
Ω).
Approximate oscillator frequency is defined by :
f=
1
C
T
(0.7 R
T
+ 3 R
D
)
.
DC transconductance (g
M
) relates to DC open-loop voltage gain (G
v
) according to the following equation : G
v
= g
M
R
L
where R
L
is the resistance
from pin 9 to ground. The minimum g
M
specification is used to calculate minimum G
v
when the error amplifier output is loaded.
4/12
MCU
京公网安备 11010802033920号
EEWORLD
