N76E003 Datasheet
Nuvoton 1T 8051-based Microcontroller
N76E003
Datasheet
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N76E003 Datasheet
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ............................................................................................................................... 5
2. FEATURES ....................................................................................................................................................... 6
3. BLOCK DIAGRAM............................................................................................................................................ 9
4. PIN CONFIGURATION ................................................................................................................................... 10
5. MEMORY ORGANIZATION ........................................................................................................................... 17
5.1 Program Memory .................................................................................................................................... 17
5.2 Data Memory .......................................................................................................................................... 19
5.3 On-Chip XRAM ....................................................................................................................................... 21
5.4 Non-Volatile Data Storage ...................................................................................................................... 21
6. SPECIAL FUNCTION REGISTER (SFR) ....................................................................................................... 22
6.1 ALL SFR DESCRIPTION ........................................................................................................................ 27
7. I/O PORT STRUCTURE AND OPERATION .................................................................................................. 85
7.1 Quasi-Bidirectional Mode ........................................................................................................................ 85
7.2 Push-Pull Mode....................................................................................................................................... 86
7.3 Input-Only Mode ..................................................................................................................................... 87
7.4 Open-Drain Mode ................................................................................................................................... 87
7.5 Read-Modify-Write Instructions .............................................................................................................. 88
7.6 Control Registers of I/O Ports ................................................................................................................. 88
7.6.1 Input and Output Data Control ..................................................................................................... 89
7.6.2 Output Mode Control .................................................................................................................... 90
7.6.3 Input Type .................................................................................................................................... 92
7.6.4 Output Slew Rate Control ............................................................................................................ 94
8. TIMER/COUNTER 0 AND 1 ............................................................................................................................ 96
8.1 Mode 0 (13-Bit Timer) ............................................................................................................................. 99
8.2 Mode 1 (16-Bit Timer) ........................................................................................................................... 100
8.3 Mode 2 (8-Bit Auto-Reload Timer) ........................................................................................................ 100
8.4 Mode 3 (Two Separate 8-Bit Timers) ................................................................................................... 101
9. TIMER 2 AND INPUT CAPTURE ................................................................................................................. 103
9.1 Auto-Reload Mode ................................................................................................................................ 107
9.2 Compare Mode ..................................................................................................................................... 108
9.3 Input Capture Module ........................................................................................................................... 108
10. TIMER 3 ...................................................................................................................................................... 114
11. WATCHDOG TIMER (WDT) ....................................................................................................................... 116
11.1 Time-Out Reset Timer ........................................................................................................................ 118
11.2 General Purpose Timer ...................................................................................................................... 119
12. SELF WAKE-UP TIMER (WKT) ................................................................................................................. 121
13. SERIAL PORT (UART) ............................................................................................................................... 123
13.1 Mode 0 ................................................................................................................................................ 128
13.2 Mode 1 ................................................................................................................................................ 129
13.3 Mode 2 ................................................................................................................................................ 130
13.4 Mode 3 ................................................................................................................................................ 131
13.5 Baud Rate ........................................................................................................................................... 132
13.6 Framing Error Detection ..................................................................................................................... 135
13.7 Multiprocessor Communication .......................................................................................................... 135
13.8 Automatic Address Recognition.......................................................................................................... 136
14. SERIAL PERIPHERAL INTERFACE (SPI) ................................................................................................ 140
14.1 Functional Description ........................................................................................................................ 140
14.2 Operating Modes ................................................................................................................................ 146
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14.2.1 Master Mode ............................................................................................................................ 146
14.2.2 Slave Mode .............................................................................................................................. 146
14.3 Clock Formats and Data Transfer....................................................................................................... 147
14.4 Slave Select Pin Configuration ........................................................................................................... 150
14.5 Mode Fault Detection .......................................................................................................................... 150
14.6 Write Collision Error ............................................................................................................................ 150
14.7 Overrun Error ...................................................................................................................................... 151
14.8 SPI Interrupt ........................................................................................................................................ 151
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15. INTER-INTEGRATED CIRCUIT (I C) ......................................................................................................... 153
15.1 Functional Description ........................................................................................................................ 153
15.1.1 START and STOP Condition ................................................................................................... 154
15.1.2 7-Bit Address with Data Format ............................................................................................... 155
15.1.3 Acknowledge ............................................................................................................................ 156
15.1.4 Arbitration ................................................................................................................................. 156
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15.2 Control Registers of I C ...................................................................................................................... 157
15.3 Operating Modes ................................................................................................................................ 161
15.3.1 Master Transmitter Mode ......................................................................................................... 161
15.3.2 Master Receiver Mode ............................................................................................................. 162
15.3.3 Slave Receiver Mode ............................................................................................................... 163
15.3.4 Slave Transmitter Mode ........................................................................................................... 164
15.3.5 General Call ............................................................................................................................. 165
15.3.6 Miscellaneous States ............................................................................................................... 166
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15.4 Typical Structure of I C Interrupt Service Routine .............................................................................. 168
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15.5 I C Time-Out ....................................................................................................................................... 172
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15.6 I C Interrupt ......................................................................................................................................... 173
16. PIN INTERRUPT ......................................................................................................................................... 174
17. PULSE WIDTH MODULATED (PWM) ....................................................................................................... 177
17.1 Functional Description ........................................................................................................................ 177
17.1.1 PWM Generator ....................................................................................................................... 177
17.1.2 PWM Types ............................................................................................................................. 186
17.1.3 Operation Modes ..................................................................................................................... 188
17.1.4 Mask Output Control ................................................................................................................ 191
17.1.5 Fault Brake ............................................................................................................................... 192
17.1.6 Polarity Control ........................................................................................................................ 193
17.2 PWM Interrupt ..................................................................................................................................... 194
18. 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) ................................................................................ 196
18.1 Functional Description ........................................................................................................................ 196
18.1.1 ADC Operation ......................................................................................................................... 196
18.1.2 ADC Conversion Triggered by External Source ...................................................................... 197
18.1.3 ADC Conversion Result Comparator ....................................................................................... 198
18.1.4 Internal Band-gap .................................................................................................................... 199
18.2 Control Registers of ADC ................................................................................................................... 202
19. TIMED ACCESS PROTECTION (TA) ........................................................................................................ 206
20. INTERRUPT SYSTEM ................................................................................................................................ 208
20.1 Interrupt Overview .............................................................................................................................. 208
20.2 Enabling Interrupts .............................................................................................................................. 209
20.3 Interrupt Priorities ............................................................................................................................... 212
20.4 Interrupt Service ................................................................................................................................. 216
20.5 Interrupt Latency ................................................................................................................................. 217
20.6 External Interrupt Pins ........................................................................................................................ 217
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21. IN-APPLICATION-PROGRAMMING (IAP) ................................................................................................ 219
21.1 IAP Commands ................................................................................................................................... 222
21.2 IAP User Guide ................................................................................................................................... 223
21.3 Using Flash Memory as Data Storage ................................................................................................ 223
21.4 In-System-Programming (ISP)............................................................................................................ 225
22. POWER MANAGEMENT ............................................................................................................................ 230
22.1 Power-Down Mode ............................................................................................................................. 231
23. CLOCK SYSTEM ........................................................................................................................................ 232
23.1 System Clock Sources ........................................................................................................................ 232
23.1.1 Internal Oscillators ................................................................................................................... 232
23.2 System Clock Switching ..................................................................................................................... 233
23.3 System Clock Divider .......................................................................................................................... 235
23.4 System Clock Output .......................................................................................................................... 235
24. POWER MONITORING .............................................................................................................................. 237
24.1 Power-On Reset (POR) ...................................................................................................................... 237
24.2 Brown-Out Detection (BOD) ............................................................................................................... 238
25. RESET ......................................................................................................................................................... 243
25.1 Power-On Reset ................................................................................................................................. 243
25.2 Brown-Out Reset ................................................................................................................................ 243
25.3 External Reset .................................................................................................................................... 244
25.4 Hard Fault Reset ................................................................................................................................. 245
25.5 Watchdog Timer Reset ....................................................................................................................... 245
25.6 Software Reset ................................................................................................................................... 246
25.7 Boot Select.......................................................................................................................................... 247
25.8 Reset State ......................................................................................................................................... 248
26. AUXILIARY FEATURES ............................................................................................................................. 249
26.1 Dual DPTRs ........................................................................................................................................ 249
26.2 96-bit UID ............................................................................................................................................ 250
27. ON-CHIP-DEBUGGER (OCD) .................................................................................................................... 251
27.1 Functional Description ........................................................................................................................ 251
27.2 Limitation of OCD ............................................................................................................................... 251
28. CONFIG BYTES.......................................................................................................................................... 253
29. IN-CIRCUIT-PROGRAMMING (ICP) .......................................................................................................... 256
30. INSTRUCTION SET .................................................................................................................................... 257
31. ELECTRICAL CHARACTERISTICS .......................................................................................................... 261
31.1 Absolute Maximum Ratings ................................................................................................................ 261
31.2 D.C. Electrical Characteristics ............................................................................................................ 261
31.3 A.C. Electrical Characteristics ............................................................................................................ 263
31.4 Analog Electrical Characteristics ........................................................................................................ 266
31.5 ESD Characteristics ............................................................................................................................ 267
31.6 EFT Characteristics ............................................................................................................................ 267
31.7 Flash DC Electrical Characteristics .................................................................................................... 268
32. PACKAGE DIMENSIONS ........................................................................................................................... 269
32.1 20-pin TSSOP – 4.4 X 6.5 mm ........................................................................................................... 269
32.2 20-pin SOP - 300 mil .......................................................................................................................... 270
32.3 20-pin QFN 3.0 X 3.0 mm for N76E003AQ20 .................................................................................... 271
32.4 20-pin QFN 3.0 X 3.0 mm for N76E003BQ20 .................................................................................... 272
32.5 20-pin QFN 3.0 X 3.0 mm for N76E003CQ20 .................................................................................... 274
33. DOCUMENT REVISION HISTORY ............................................................................................................ 275
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1. GENERAL DESCRIPTION
The N76E003 is an embedded flash type, 8-bit high performance 1T 8051-based microcontroller. The
instruction set is fully compatible with the standard 80C51 and performance enhanced.
The N76E003 contains a up to 18K Bytes of main Flash called APROM, in which the contents of User
Code resides. The N76E003 Flash supports In-Application-Programming (IAP) function, which
enables on-chip firmware updates. IAP also makes it possible to configure any block of User Code
array to be used as non-volatile data storage, which is written by IAP and read by IAP or MOVC
instruction. There is an additional Flash called LDROM, in which the Boot Code normally resides for
carrying out In-System-Programming (ISP). The LDROM size is configurable with a maximum of 4K
Bytes. To facilitate programming and verification, the Flash allows to be programmed and read
electronically by parallel Writer or In-Circuit-Programming (ICP). Once the code is confirmed, user can
lock the code for security.
The N76E003 provides rich peripherals including 256 Bytes of SRAM, 768 Bytes of auxiliary RAM
(XRAM), Up to 18 general purpose I/O, two 16-bit Timers/Counters 0/1, one 16-bit Timer2 with three-
channel input capture module, one Watchdog Timer (WDT), one Self Wake-up Timer (WKT), one 16-
bit auto-reload Timer3 for general purpose or baud rate generator, two UARTs with frame error
detection and automatic address recognition, one SPI, one I C, five enhanced PWM output channels,
eight-channel shared pin interrupt for all I/O, and one 12-bit ADC. The peripherals are equipped with
18 sources with 4-level-priority interrupts capability.
The N76E003 is equipped with three clock sources and supports switching on-the-fly via software. The
three clock sources include external clock input, 10 kHz internal oscillator, and one 16 MHz internal
precise oscillator that is factory trimmed to ±1% at room temperature. The N76E003 provides
additional power monitoring detection such as power-on reset and 4-level brown-out detection, which
stabilizes the power-on/off sequence for a high reliability system design.
The N76E003 microcontroller operation consumes a very low power with two economic power modes
to reduce power consumption
－
Idle and Power-down mode, which are software selectable. Idle
mode turns off the CPU clock but allows continuing peripheral operation. Power-down mode stops the
whole system clock for minimum power consumption. The system clock of the N76E003 can also be
slowed down by software clock divider, which allows for a flexibility between execution performance
and power consumption.
With high performance CPU core and rich well-designed peripherals, the N76E003 benefits to meet a
general purpose, home appliances, or motor control system accomplishment.
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