PSD4235G1V-A-20B81I datasheet, PDF

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PSD4235G1V-A-20B81I: Description4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80; Categorysemiconductor The embedded processor and controller; File Size747KB，129 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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PSD4235G1V-A-20B81I Overview

4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80

PSD4235G1V-A-20B81I Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	80
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	3 V
Rated supply voltage	3.3 V
Number of input and output buses	52
Processing package description	Plastic, TQFP-80
state	DISCONTINUED
packaging shape	SQUARE
Package Size	FLATPACK, THIN PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
Microprocessor type	Universal PIA
Number of ports	7

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PSD4235G2

Flash in-system programmable (ISP)

for 16-bit MCUs (5 V supply)

Features

■

Dual bank Flash memories

– 4 Mbit of Primary Flash memory (8 uniform

sectors, 32K x 16)

– 256 Kbit Secondary Flash memory with 4

sectors

– Concurrent operation: read from one

memory while erasing and writing the other

64 Kbit SRAM

PLD with macrocells

– Over 3000 gates of PLD: CPLD and DPLD

– CPLD with 16 output macrocells (OMCs)

and 24 input macrocells (IMCs)

– DPLD - user defined internal chip select

decoding

7 L/O ports with 52 I/O pins

– 52 individually configurable I/O port pins

that can be used for the following functions:

– MCU I/Os

– PLD I/Os

– Latched MCU address output

– Special function l/Os

– l/O ports may be configured as open-drain

outputs

In-system programming (ISP) with JTAG

– Built-in JTAG compliant serial port allows

full-chip In-System Programmability

– Efficient manufacturing allow easy product

testing and programmingUse low cost

FlashLINK cable with PC

■

LQFP80 (U)

80-lead, Thin, Quad, Flat

■

Page register

– Internal page register that can be used to

expand the microcontroller address space

by a factor of 256

– Programmable power management

High endurance

– 100,000 Erase/write c ycles of Flash

memory

– 1,000 Erase/WRITE Cycles of PLD

– 15 Year Data Retention

Single supply voltage

– 5V ±10%

Memory speed

– 70ns Flash memory and SRAM access

time

Packages are ECOPACK

●

■

February 2009

Rev 4

1/129

www.st.com

Contents

PSD4235G2

Contents

Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.1

In-system programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.1.1

1.1.2

1.1.3

First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . 12

Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2

In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2.1

1.2.2

1.2.3

Simultaneous READ and WRITE to Flash memory . . . . . . . . . . . . . . . . 13

Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Separate Program and Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.3

PSDsoft™ Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

ISP via JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PSD register description and address offsets . . . . . . . . . . . . . . . . . . . 26

6.1

6.2

6.3

6.4

Data-In registers - port A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . 28

Data-out registers - port A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . 28

Direction registers - ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . 28

Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2/129

PSD4235G2

Contents

6.5

6.6

6.7

6.8

6.9

6.10

6.11

6.12

6.13

6.14

6.15

6.16

6.17

6.18

6.19

Drive registers - Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Drive registers - Ports C and F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Enable-Out registers - Ports A, B, C, F . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Input macrocells registers- ports A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . 29

Output macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Mask macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Flash Memory Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Flash Boot Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

JTAG Enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

PMMR0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

PMMR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

VM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Memory_ID0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Memory_ID1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.1

7.2

Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Primary Flash memory and Secondary Flash memory description . . . . . 36

7.2.1

7.2.2

Memory block Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.3

Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

8.10

Power-up condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Reading Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Read Primary Flash identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Read Memory Sector Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Reading the Erase/Program status bits . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Data Polling (DQ7) - DQ15 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Toggle flag (DQ6) - DQ14 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Error flag (DQ5) - DQ13 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Erase timeout flag (DQ3) - DQ11 for Motorola . . . . . . . . . . . . . . . . . . . . . 42

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Contents

PSD4235G2

Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.1

9.2

9.3

Data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.1

10.2

10.3

Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

11.1

11.2

11.3

Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Reset (RESET) pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Memory Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

13.1

13.2

13.3

13.4

13.5

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Memory Select configuration for MCUs with separate

Program and Data spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Combined space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

80C51XA memory map example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Memory ID registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

18.1

18.2

Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4/129

PSD4235G2

Contents

18.3

18.4

18.5

18.6

18.7

Loading and Reading the output macrocells (OMC) . . . . . . . . . . . . . . . . 64

The OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

The output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

19.1

19.2

19.3

19.4

19.5

19.6

19.7

19.8

19.9

PSD interface to a multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 71

Data Byte Enable reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

80C196 and 80C186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

MC683xx and MC68HC16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

H8/300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

MMC2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

19.10 C16x family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

20.1

20.2

20.3

20.4

20.5

20.6

20.7

20.8

20.9

General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Data Port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

20.10 MCU Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

20.11 Port Configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

20.12 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

20.13 Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

20.14 Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

20.15 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

5/129

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