Datasheet
Gate Driver Providing Galvanic isolation Series
Isolation voltage 2500Vrms
1ch Gate Driver Providing Galvanic Isolation
BM6104FV-C
General Description
The BM6104FV-C is a gate driver with isolation voltage
2500Vrms, I/O delay time of 150ns, and minimum input
pulse width of 90ns, and incorporates the fault signal
output functions, undervoltage lockout (UVLO) function,
and short current protection (SCP, DESAT) function.
Key Specifications
Isolation Voltage:
Maximum Gate Drive Voltage:
I/O Delay Time:
Minimum Input Pulse Width:
2500Vrms
24V
150ns(Max)
90ns(Max)
Package
Features
Providing Galvanic Isolation
Active Miller Clamping
Fault Signal Output Function
(Adjustable Output Holding Time)
Undervoltage Lockout Function
Short Current Protection Function
(Adjustable Reset Time)
Soft Turn-Off Function For Short Current Protection
(Adjustable Turn-Off Time)
Supporting Negative VEE2
Output State Feedback Function
UL1577 Recognized:File No. E356010
AEC-Q100 Qualified
(Note 1)
(Note 1:Grade1)
SSOP-B20W
W(Typ) x D(Typ) x H(Max)
6.50mm x 8.10mm x 2.01mm
Applications
IGBT Gate Driver
MOSFET Gate Driver
Typical Application Circuits
GND1
OSFB
INB
FLTRLS
VCC1
INA
+
S
Q
R
Timer
PROOUT
VEE2
Latch
ENA
-
FB
+
-
OUT1L
OUT1H
VCC2
FLT
UVLO
FLT
INA
ENA
TEST
GND1
UVLO
Regulator
LOGIC
VREG
OUT2
LOGIC
S
Q
R
GND2
+
VEE2
SCPIN
-
Figure 1. For using 4-pin IGBT (for using SCP function)
1pin
GND1
OSFB
INB
FLTRLS
VCC1
INA
+
S
Q
R
Timer
PROOUT
VEE2
Latch
ENA
-
FB
+
-
OUT1L
OUT1H
VCC2
FLT
UVLO
FLT
INA
ENA
TEST
GND1
UVLO
Regulator
LOGIC
VREG
OUT2
LOGIC
S
Q
R
GND2
+
VEE2
SCPIN
-
Figure 2. For using 3-pin IGBT (for using DESAT function)
1pin
○Product
structure：Silicon integrated circuit
○This
product is not designed protection against radioactive rays
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BM6104FV-C
Recommended Range Of External Constants
Pin Name
FLTRLS
VREG
VCC1
VCC2
Symbol
C
FLTRLS
R
FLTRLS
C
VREG
C
VCC1
C
VCC2
Recommended Value
Min
-
50
1.0
0.1
0.33
Typ
0.01
200
3.3
1.0
-
Max
0.47
1000
10.0
-
-
Unit
µF
kΩ
µF
µF
µF
Pin Configurations
(TOP VIEW)
SCPIN
VEE2
GND2
OUT2
VREG
VCC2
OUT1H
OUT1L
VEE2
1
2
3
4
5
6
7
8
9
20
8
19
8
18
8
17
8
16
8
15
8
14
8
13
8
12
8
11
8
GND1
TEST
ENA
INA
FLT
VCC1
FLTRLS
INB
OSFB
GND1
PROOUT 10
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
SCPIN
VEE2
GND2
OUT2
VREG
VCC2
OUT1H
OUT1L
VEE2
PROOUT
GND1
OSFB
INB
FLTRLS
VCC1
FLT
INA
ENA
TEST
GND1
Short current detection pin
Output-side negative power supply pin
Output-side ground pin
MOSFET control pin for Miller Clamp
Power supply pin for driving MOSFET for Miller Clamp
Output-side positive power supply pin
Source side output pin
Sink side output pin
Output-side negative power supply pin
Soft turn-off pin
Input-side ground pin
Output state feedback output pin
Control input pin B
Fault output holding time setting pin
Input-side power supply pin
Fault output pin
Control input pin A
Input enabling signal input pin
Mode setting pin
Input-side ground pin
Function
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Description of pins and cautions on layout of board
1) VCC1 (Input-side power supply pin)
The VCC1 pin is a power supply pin on the input side. To suppress voltage fluctuations due to the current to drive internal
transformers, connect a bypass capacitor between the VCC1 and the GND1 pins.
2) GND1 (Input-side ground pin)
The GND1 pin is a ground pin on the input side.
3) VCC2 (Output-side positive power supply pin)
The VCC2 pin is a positive power supply pin on the output side. To reduce voltage fluctuations due to OUT1H/L pin
output current and due to the current to drive internal transformers, connect a bypass capacitor between the VCC2 and
the GND2 pins.
4) VEE2 (Output-side negative power supply pin)
The VEE2 pin is a power supply pin on the output side. To suppress voltage fluctuations due to OUT1H/L pin output current
and due to the current to drive internal transformers, connect a bypass capacitor between the VEE2 and the GND2 pins. To
use no negative power supply, connect the VEE2 pin to the GND2 pin.
5) GND2 (Output-side ground pin)
The GND2 pin is a ground pin on the output side. Connect the GND2 pin to the emitter / source of a power device.
6) IN (Control input terminal)
The IN is a pin used to determine output logic.
ENA
INB
H
X
L
H
L
H
L
L
L
L
INA
X
L
H
L
H
OUT1H
Hi-Z
Hi-Z
Hi-Z
Hi-Z
H
OUT1L
L
L
L
L
Hi-Z
7) FLT (Fault output pin)
The FLT pin is an open drain pin used to output a fault signal when a fault occurs (i.e., when the undervoltage lockout
function (UVLO) or short current protection function (SCP) is activated).
Pin
FLT
While in normal operation
Hi-Z
When an Fault occurs
L
(When UVLO or SCP is activated)
8) FLTRLS (Fault output holding time setting pin)
The FLTRLS is a pin used to make setting of time to hold a Fault signal. Connect a capacitor between the FLTRLS pin
and the GND1 pin, and a resistor between it and the VCC1 pin.
The Fault signal is held until the FLTRLS pin voltage exceeds a voltage set with the V
FLTRLS
parameter. To set holding
time to 0 ms, do not connect the capacitor. Short-circuiting the FLTRLS pin to the VCC1 pin will cause a high current to
flow in the FLTRLS pin and, in an open state, may cause the IC to malfunction. To avoid such trouble, be sure to connect
a resistor between the FLTRLS and the VCC1 pins.
9) OUT1H, OUT1L (Output pin)
The OUT1H pin is a source side pin used to drive the gate of a power device, and the OUT1L pin is a sink side pin
used to drive the gate of a power device.
10) OUT2 (MOSFET control pin for Miller Clamp)
The OUT2 is a pin for controlling the external MOS switch to prevent the increase in gate voltage due to the miller
current of the power device connected to OUT1H/L pin.
11) VREG (Power supply pin for driving the MOSFET for Miller Clamp)
The VREG pin is a power supply pin for Miller Clamp (typ 10V). Be sure to connect a capacitor between VREG pin and
VEE2 pin to prevent oscillation and to reduce voltage fluctuations due to OUT2 pin output current.
12) PROOUT (Soft turn-off pin)
The PROOUT is a pin used to put the soft turn-off function of a power device in operation when the SCP function is
activated. This pin combines with the gate voltage monitoring pin for Miller Clamp function and OSFB function which
output the gate state.
13) SCPIN (Short current detection pin)
The SCPIN is a pin used to detect current for short current protection. When the SCPIN pin voltage exceeds V
SCDET
(typ 0.7V), the SCP function will be activated. This may cause the IC to malfunction in an open state. To avoid such
trouble, short-circuit the SCPIN pin to the GND2 pin if the short current protection is not used. In order to prevent the
wrong detection due to noise, the noise mask time t
SCPMSK
(typ 0.8µs) is set.
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14) OSFB (Output state feedback output pin)
The OSFB pin is an open drain pin used to output the gate state. If the IN and the OUT1H/L pin are at the same level,
the OSFB pin output the “Hi-Z” level, otherwise the OSFB pin output the “L” level and hold “L” until ENA=H or UVLO on
low voltage side is activated.
15) TEST(Mode setting pin)
The TEST pin is an operation mode setting pin. This pin is usually connected to GND1 pin. If the TEST pin is
connected to the VCC1 pin, Input-side UVLO function is disabled.
Description of functions and examples of constant setting
1) Miller Clamp function
When OUT1H/L=Hi-Z/L and PROOUT pin voltage < V
OUT2ON
(typ 2V), H is output from OUT2 pin and the external MOS
switch is turned ON. When OUT1H/L=H/Hi-Z, L is output from OUT2 pin and the external MOS switch is turned OFF.
While the short-circuit protection function is activated, L is output from OUT2 pin and the external MOS switch is turned
OFF.
Short current
Detected
SCPIN
Not less than
V
SCDET
X
Not detected
X
X
IN
X
L
L
H
VCC2
PREDRIV ER
PREDRIV ER
PROOUT
LOGIC
PREDRIV ER
REGULATOR
PREDRIV ER
PREDRIV ER
+
+
+
+
+
+
+
-
PROOUT
X
Not less than V
OUT2ON
less than V
OUT2ON
X
OUT2
L
L
H
L
OUT1H/L
VREG
OUT2
V
OUT2ON
GND2
VEE2
Figure 3. Block diagram of Miller Clamp function.
t
POFF
(typ 115ns)
IN
t
PON
(typ 115ns)
OUT1H/L
PROOUT
(Monitor the gate voltage)
t
OUT2ON
(typ 25ns)
OUT2
Figure 4. Timing chart of Miller Clamp function
V
OUT2ON
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BM6104FV-C
2) Fault status output
This function is used to output a fault signal from the FLT pin when a fault occurs (i.e., when the undervoltage lockout
function (UVLO) or short current protection function (SCP) is activated) and hold the Fault signal until the set Fault output
holding time is completed. The Fault output holding time t
FLTRLS
is given as the following equation with the settings of
capacitor C
FLTRLS
and resistor R
FLTRLS
connected to the FLTRLS pin. For example, when C
FLTRLS
is set to 0.01
F and
R
FLTRLS
is set to 200k, the holding time will be set to 2 ms.
t
FLTRLS
[ms]= C
FLTRLS
[µF]•R
FLTRLS
[k]
To set the fault output holding time to “0” ms, only connect the resistor R
FLTRLS
.
Status
Normal
Fault occurs
FLT pin
Hi-Z
L
Status
Fault occurs (The UVLO or SCP function is activated.)
UVLO
V
FLTRLS
FLTRLS
VCC1
FLT
SCP
S
R
FLT
L
H
OUT1H/L
L
Fault output holding time (t
FLTRLS
)
C
FLTRLS
R
FLTRLS
Hi-Z
FLTRLS
-
+
FLT
GND1
ECU
Figure 5. Fault Status Output Timing Chart
Figure 6. Fault Output Block Diagram
3) Undervoltage Lockout (UVLO) function
The BM6104FV-C incorporates the undervoltage lockout (UVLO) function both on the low and the high voltage sides.
When the power supply voltage drops to the UVLO ON voltage (low voltage side typ 3.4V, high voltage side typ 9.05V),
the OUT1 and the FLT pin both will output the “L” signal. When the power supply voltage rises to the UVLO OFF voltage
(low voltage side typ 3.5V, high voltage side typ 9.55V), these pins will be reset. However, during the fault output holding
time set in “2) Fault status output” section, the OUT1 pin and the FLT pin will hold the “L” signal. In addition, to prevent
malfunctions due to noises, mask time t
UVLO1MSK
(typ 10µs) and t
UVLO2MSK
(typ 10µs) are set on both low and high
voltage sides.
IN
H
L
V
UVLO1H
V
UVLO1L
VCC1
FLT
OUT1H/L
Figure 7. Low voltage side UVLO Function Operation Timing Chart
IN
Hi-Z
L
H
L
H
L
V
UVLO2H
V
UVLO2L
VCC2
FLT
OUT1H/L
Figure 8. High voltage side UVLO Operation Timing Chart
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L
H
Hi-Z
L
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